FREQUENCY DISTRIBUTED FLASH MEMORY ALLOCATION BASED ON FREE PAGE TABLES

• US 20090164702A1
• Filed: 12/21/2007
• Published: 06/25/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Spansion LLC (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Kern, William
• Granted Patent: US 8,656,083 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time.

Claims

1. A system for memory allocation in a computing system, comprising

a volatile memory device

a non-volatile memory device including blocks, each block having addressable physical pages;

a memory allocation module stored in the volatile memory and operable to allocate physical page address to a system address, wherein the memory allocation module includes;

system address rate logic operable to determine a frequency rate for a provided system address;

erase cycle state logic operable to determine an erase cycle state for each block in the non-volatile memory device; and

address assignment logic operable to assign a physical page address to the system address based on the determined frequency rate at which the system address is written and the erase cycle state of a block from which the physical page resides.

2. The system of claim 1, wherein the system address rate logic is further operable to determine a number of times in which a system address is written over a predetermined period of time.

3. The system of claim 1, wherein the system address rate logic is further operable to determine the frequency rate by recording a count of write operations for a translation table offset and dividing the count by a predetermined time interval.

4. The system of claim 1, wherein the erase cycle state logic is further operable to record a quantity of erase cycles that each addressable block has encountered.

5. The system of claim 1, wherein the erase cycle state logic is further operable to determine an erase cycles state by recording in an erase block table a number of erase operations that a block has received, a history of frequency use for the block and a current use frequency for the block.

6. The system of claim 1, wherein the address assignment logic is further operable to assign a physical page address to the system address such that the frequency rate at which the system address is written is inversely proportional to the erase cycle state of the block from which the physical page resides.

7. The system of claim 1, wherein the memory allocation module further comprises block pooling logic operable to group addressable blocks in two or more allocation pools, wherein each pool reflects addressable blocks having different thresholds of erase cycle states.

8. The system of claim 7, wherein the address assignment logic is further operable to select a pool from which to assign a physical page address based on the determined frequency rate at which the system address is written and the erase cycle state thresholds for the pools.

9. The system of claim 7, wherein the address assignment logic is further operable to assign a physical page address from a pool having a use frequency directly proportional to the determined frequency rate at which the system address is written.

10. The system of claim 7, wherein the block pooling logic is further operable to dynamically re-assign blocks to different pools based on the erase cycle state of each block.

11. An electronic device comprising the system of claim 1.

12. The electronic device of claim 11, the electronic device is one of a computer, a cellular phone, a digital phone, a video device, a smart card, a personal digital assistant, a television, an electronic game, a digital camera, an electronic organizer, an audio player, an audio recorder, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), an electronic control unit associated with a motor vehicle, a global positioning satellite (GPS) device, an electronic device associated with an airplane, an electronic device associated with an industrial control system, a Hardware Security Module (HSM), a set-top box, a secure memory device with computational capabilities, or an electronic device with at least one tamper-resistant chip.

13. A method for memory allocation in a non-volatile memory device, comprising:

providing for a system address;

determining a frequency rate at which the system address is written;

determining an erase cycle state for each addressable block; and

assigning a physical page address to the system address based on the determined frequency rate at which the system address is written and the erase cycle state of a block from which the physical page resides.

14. The method of claim 13, wherein determining a frequency rate at which a system address is written further comprises determining a number of times in which a system address is written over a predetermined period of time.

15. The method of claim 13, wherein determining an erase cycle state further comprises recording a quantity of erase cycles that each addressable block has encountered.

16. The method of claim 13, wherein assigning a physical page address to the system address further comprises assigning a physical page address to the system address such that the frequency rate at which the system address is written is inversely proportional to the erase cycle state of the block from which the physical page resides.

17. The method of claim 13, further comprising grouping addressable blocks in two or more allocation pools wherein each pool reflects addressable blocks having different thresholds of erase cycle states.

18. The method of claim 17, wherein assigning a physical page address to the system address further comprises selecting a pool from which to assign a physical page address based on the determined frequency rate at which the system address is written and the erase cycle state thresholds for the pools.

19. The method of claim 17, assigning a physical page address to the system address further comprises assigning a physical page address from a pool having a use frequency directly proportional to the determined frequency rate at which the system address is written.

20. The method of claim 17, further comprising dynamically re-assigning blocks to different pools based on the erase cycle state of each block.