Programmable Address Processor for Graphics Applications

• US 20090164726A1
• Filed: 12/20/2007
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: SKOWRONEK, Stanislaw K.
• Granted Patent: US 8,037,256 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Methods and systems for processing memory lookup requests are provided. In an embodiment, an address processing unit includes an instructions module configured to store instructions to be executed to complete a primary memory lookup request and a logic unit coupled to the instructions module. The primary memory lookup request is associated with a desired address. Based on an instruction stored in the instructions module, the logic unit is configured to generate a secondary memory lookup request that requests the desired address.

In another embodiment, a method of processing memory lookups requests includes receiving a primary memory lookup request that corresponds to a desired memory address and generating a plurality of secondary memory lookup requests.

Claims

1. An apparatus, comprising:

an instructions module configured to store instructions to be executed to complete a primary memory lookup request; and

a logic unit coupled to the instructions module;

wherein the primary memory lookup request is associated with a desired address and wherein based on an instruction stored in the instructions module, the logic unit is configured to generate a secondary memory lookup request that requests the desired address.

2. The apparatus of claim 1, further comprising:

a first in first out (FIFO) buffer configured to hold an entry that holds at least a portion of a result of a second secondary memory lookup request; and

a read holding register configured to hold an entry that includes at least a portion of an entry held in the FIFO buffer.

3. The apparatus of claim 2, wherein the first entry of the read holding register holds a first memory address and a second entry of the read holding register holds a second memory address, wherein the first memory address and the second memory address are related.

4. The apparatus of claim 2, wherein the buffer is configured to intercept the results of the second secondary memory lookup request and wherein the buffer is configured not to intercept results of the first secondary memory request.

5. The apparatus of claim 1, further comprising:

a parameter memory configured to store constants that are used to complete the primary memory lookup request; and

a plurality of registers that are operated upon by the logic unit.

6. The apparatus of claim 1, wherein the instructions module comprises:

a program memory configured to store instructions; and

an instructions control module configured to select instructions from the program memory to be executed by the logic unit;

wherein the instructions control module is configured to select instructions for the primary lookup request based on a type associated with the primary lookup request and a program counter.

7. The apparatus of claim 1, further comprising a request queue configured to hold threads corresponding to primary memory lookup requests, wherein the request queue is a re-order request queue configured to order threads so that returns to primary memory lookup requests are provided in a desired order.

8. The apparatus of claim 1, further comprising:

an input module configured to receive the primary memory lookup request,

wherein the input module processes the primary memory lookup request to determine an associated type, and

wherein the input module is coupled to the instructions module.

9. The apparatus of claim 1, wherein the apparatus is configured to receive a plurality of primary memory lookup requests, further comprising a thread selection module configured to select a thread associated with a primary memory lookup request of the primary memory lookup requests based on an available capacity of at least one of a request queue or a buffer or based on at least one of a probability that the request queue will overflow or a probability that the buffer will overflow.

10. A method of processing memory lookups requests, comprising:

(a) receiving a primary memory lookup request that corresponds to a desired memory address; and

(b) generating a plurality of secondary memory lookup requests, wherein each secondary memory lookup request of the plurality of secondary memory lookup requests is associated with the primary memory lookup request;

wherein a secondary memory lookup request of the plurality of secondary memory lookup requests corresponds to the desired address.

11. The method of claim 10, wherein a second secondary memory lookup request corresponds to a first memory address and a third secondary memory lookup request corresponds to a second memory address, wherein the third secondary memory lookup request is generated based on at least the first memory address.

12. The method of claim 10, further comprising:

(c) classifying the primary memory lookup request as a memory lookup type; and

(d) generating a thread corresponding to the primary memory lookup request.

13. The method of claim 12, further comprising:

(e) allocating register space to the thread; and

(f) loading relevant information into registers of the allocated register space.

14. The method of claim 13, wherein the initial values are determined based at least on the desired memory address and the memory lookup type.

15. The method of claim 12, wherein step (b) comprises:

selecting a instruction from an instruction memory based on the memory lookup type; and

executing the instruction, wherein the instruction results in a second secondary memory lookup request being generated.

16. The method of claim 15, further comprising:

(e) receiving a second primary memory lookup request;

(f) classifying the second primary memory lookup request as a second memory lookup type;

(g) generating a second thread corresponding to the second primary memory lookup request; and

(h) generating a second plurality of secondary memory lookup requests, wherein each secondary memory lookup request of the second plurality of secondary memory lookup requests is associated with the second primary memory lookup request.

17. The method of claim 16, further comprising:

(i) holding the second thread in a request queue, wherein the request queue also holds the first thread.

18. The method of claim 16, wherein step (h) comprises:

selecting the second thread for execution;

selecting a second instruction from the instruction memory based on the second memory lookup type; and

executing the second instruction, wherein the second instruction results in a second secondary memory lookup request being generated.

19. The method of claim 18, further comprising:

(j) receiving at least a portion of a result of the second secondary memory lookup request in an entry of a buffer;

wherein step (b) comprises;

selecting the first thread for execution;

loading at least a portion of the entry into at least one register in the allocated register space;

selecting a third instruction from an instruction memory based on the first memory lookup type; and

executing the third instruction, wherein the instruction results in a third secondary memory lookup being executed.

20. The method of claim 19, wherein the third secondary memory lookup requests the desired address.

21. The method of claim 10, wherein step (b) comprises:

designating the secondary memory lookup request of the plurality of secondary memory lookup requests as a final memory lookup request.

22. A system, comprising:

a memory; and

an address processing unit (APU) coupled to the memory and configured to receive a primary memory lookup request corresponding to a desired address in the memory and to generate a plurality of secondary memory lookup requests, wherein each secondary memory lookup request of the plurality of secondary memory lookup requests is associated with the desired address.

23. The system of claim 22, further comprising:

a second memory;

wherein the APU is configured to receive a memory lookup miss of the second memory as the primary memory lookup request.

24. The system of claim 23, wherein at least one of the first memory and the second memory is a cache.