Method,system and apparatus for handling events for partitions in a socket with sub-socket partitioning

• US 20090164739A1
• Filed: 11/07/2008
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thomas, Tessil, Harikumar, Ajay, Simon, Biju Puthur
• Granted Patent: US 8,635,380 B2
• Time in Patent Office: Days
• US Class Current: 711/153
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 2209/543 Local
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.

Claims

1. A method comprising:

defining a plurality of partitions within a socket for sub-socket partitioning;

receiving an event; and

isolating the event to a partition within the socket.

2. The method of claim 1 wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition.

3. The method of claim 2 wherein the reset is a partition specific reset.

4. The method of claim 3 wherein the partition specific reset is performed by a system service processor (SSP) by first setting a reset enable bit of an impacted shared resource and then asserting a global system reset.

5. The method of claim 3 wherein the partition specific reset is performed by software initiating a write operation into a register into an input/output controller (ICH).

6. The method of claim 3 wherein the partition specific reset is performed by an input/output hub (IOH) activating a reset wire to a socket and to an input/output device.

7. The method of claim 2 wherein the error is classified into either a partition specific notice or a system wide notice.

8. A system comprising:

a processor within a socket and having a plurality of cores;

a dynamic random access memory, coupled to the processor, to receive requests from the processor;

the processor to support sub-soc7ket partitioning to utilize at least a first operating system and a second operating system within a first partition and a second partition; and

the processor to receive an event and to isolate the event to either the first partition or the second partition within the socket.

9. The system of claim 8 wherein the event is a reset, interrupt, error, or reliability, availability, and serviceability (RAS) condition.

10. The system of claim 9 wherein the reset is a partition specific reset.

11. The system of claim 8 further comprising a system service processor (SSP).

12. The system of claim 11 wherein the SSP is to facilitate the partition specific reset by first setting a reset enable bit of an impacted shared resource and then asserting a global system reset.

13. The system of claim 8 further comprising an interrupt logic, coupled to the processor, to facilitate an interrupt.

14. The system of claim 13 wherein the interrupt logic is to issue a message with a partition identifier to determine whether a receiving core is in the same socket or a different socket.

15. A processor comprising:

a plurality of processor cores that support sub-socket partitioning that allows a plurality of partitions;

the processor to receive an interrupt; and

an interrupt logic, coupled to the processor, to facilitate handling of the interrupt by isolating the interrupt to a partition of the plurality of partitions.

16. The processor of claim 15 wherein the interrupt logic is to issue a message with a partition identifier to determine whether a receiving core is in the same socket or a different socket.

17. The processor of claim 15 wherein the interrupt logic is to facilitate an interrupt.