Memory access protection

• US 20090164744A1
• Filed: 12/24/2007
• Published: 06/25/2009
• Est. Priority Date: 12/24/2007
• Status: Abandoned Application

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Application Number:
  US12/004,734
• Publication Number:
  US 20090164744A1
• Time in Patent Office: Days
• US Class Current: 711/164
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A memory system is provided. The memory system includes a memory array and a memory controller in communication with the memory array. The memory controller is configured to receive a first password and to compare the first password with a second password. The second password is stored in the memory controller. If the first password matches the second password, then access is permitted to the memory array. The memory array can include a plurality of vertically stacked memory arrays. The vertically stacked memory arrays can be formed on top of a logic plane that includes active circuitry in communication with the vertically stacked memory arrays. The memory arrays can include two-terminal memory cells that store data as a plurality of conductivity profiles and retain the stored data in the absence of power. The memory arrays may be configured as non-volatile two-terminal cross-point memory arrays.

Claims

1. A memory system, comprising:

a memory array; and

a memory controller in communication with the memory array, the memory controller being configured to

receive a first password,

compare the first password with a second password, the second password being stored in the memory controller, and

permit access to the memory array if the first password matches the second password.

2. The memory system of claim 1, wherein the access is permitted to only a portion of the memory array.

3. The memory system of claim 1, wherein the memory controller is further configured to:

receive a memory address; and

retrieve the second password based on the memory address.

4. The memory system of claim 1, wherein the memory array comprises a third dimension memory array.

5. A memory system, comprising:

a memory array;

a first memory configured to receive a first memory address, the first memory address including a master password;

a second memory configured to store a first temporary password; and

a first comparator in communication with the memory array, the first memory, and the second memory, the first comparator being configured to compare the master password with the first temporary password.

6. The memory system of claim 5, wherein a match of the master password and the first temporary password permits access to the memory array.

7. The memory system of claim 5, wherein the first temporary password is associated with the first memory address.

8. The memory system of claim 5, wherein the first memory is configured to receive a second temporary password, the memory system further comprising:

a third memory in communication with the first comparator, the third memory being configured to store an access password, the access password being associated with a portion of the memory array; and

a second comparator in communication with the first memory, the third memory, and the memory array, the second comparator being configured to compare the second temporary password with the access password.

9. The memory system of claim 8, wherein the portion of the memory array is a memory block.

10. The memory system of claim 8, wherein a match of the second temporary password and the access password permits access to the portion of the memory array.

11. The memory system of claim 5, wherein the memory array comprises a third dimension memory array.

12. A memory system, comprising:

a third dimension memory array;

a first memory configured to receive a first memory address, the first memory address including a first password;

a second memory configured to store a second password associated with the first memory address; and

a first comparator including a first input, a second input, and an output, the first input being in communication with the first memory, the second input being in communication with the second memory, the output being in communication with the third dimension memory array, the first comparator being configured to compare the first password with the second password.

13. The memory system of claim 12, wherein the first memory and the second memory are registers.

14. The memory system of claim 12, wherein the third dimension memory array includes a plurality of non-volatile two-terminal cross-point memory arrays that are vertically stacked upon each other.

15. A memory system, comprising:

a third dimension memory array;

a first memory configured to receive a first memory address, the first memory address including a first password;

a second memory configured to store a second password, the second password being associated with the first memory address;

a third memory configured to store a third password;

a first comparator in communication with the third dimension memory array, the first memory, and the second memory, the first comparator being configured to compare the first password with the second password; and

a second comparator in communication with the first memory and the third memory.

16. The memory system of claim 15, wherein the first memory is further configured to receive a second memory address, the second memory address including a fourth password, and wherein the second comparator is configured to compare the fourth password with the third password.

17. The memory system of claim 15, wherein the first comparator includes a first input, a second input, and an output, the first input being in communication with the first memory, the second input being in communication with the second memory, the output being in communication with the third dimension memory array.

18. The memory system of claim 15, wherein the second comparator includes a first input, a second input, and an output, the first input being in communication with the first memory, the second input being in communication with the third memory, the output being in communication with the second memory.

19. The memory system of claim 15, wherein the second comparator is configured to output an enable signal to the second memory, the enable signal enabling the first comparator to compare the first password with the second password.

20. The memory system of claim 15, wherein the third dimension memory array includes a plurality of non-volatile two-terminal cross-point memory arrays that are vertically stacked upon each other.