Self-configurable multi-regulator ASIC core power delivery

• US 20090164807A1
• Filed: 12/21/2007
• Published: 06/25/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chi, Steve X., Nguyen, Daniel P., Lai, Po-Shen, Wang, Yongliang, Condito, Vincent Anthony, Bhuiyan, Ekram Hossain
• Granted Patent: US 7,859,134 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Claims

1. A method for operating an electronic apparatus, the apparatus including an ASIC device, a linear regulator module configured to be optionally coupled to an external-to-the-ASIC device capacitor via a node and a capless regulator module coupled to an internal capacitance of the electronic product via the node, the capless regulator module including a low-power sub-module and a high-power sub-module, the high-power sub-module configured to provide a greater amount of electrical current than the low-power sub-module, the method comprising:

applying power initially to the ASIC device via the node with the low-power sub-module of the capless regulator module to initiate ASIC device power-up; and

detecting whether or not an external capacitance is coupled to the node.

2. The method of claim 1, further comprising:

subsequently applying power to the ASIC device via the node with the high-power sub-module of the capless regulator module in response to detection of an external-to-the-ASIC device capacitor coupled to the node.

3. The method of claim 1, further comprising:

subsequently applying power to the ASIC device via the node with the low-power sub-module of the capless regulator module in response to detection of an absence of an external-to-the-ASIC device capacitor coupled to the node.

4. The method of claim 2, further comprising:

completing the power-up of the ASIC device.

5. The method of claim 3, further comprising:

completing the power-up of the ASIC device.

6. The method of claim 4, further comprising:

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device after power-up of the ASIC device.

7. The method of claim 5, further comprising:

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device after power-up of the ASIC device.

8. The method of claim 6, wherein the selecting is carried out by executing control logic in the ASIC device.

9. The method of claim 7, wherein the selecting is carried out by executing control logic in the ASIC device.

10. The method of clam 6, wherein the selecting is responsive to a stored state of a configuration register accessible by the ASIC device.

11. The method of clam 7, wherein the selecting is responsive to a stored state of a configuration register accessible by the ASIC device.

12. A method for operating a memory device, the memory device including a memory array, an interface circuit configured to communicate with a host device, a controller coupled to communicate with the memory array and the interface circuit, the controller implemented on an ASIC device, the controller including a linear regulator module configured to be optionally coupled in operation to an external-to-the-ASIC device capacitor via a node and a capless regulator module coupled to an internal capacitance of the ASIC device via the node, the capless regulator module including a low-power sub-module and a high-power sub-module, the high-power sub-module configured to provide a greater amount of electrical current than the low-power sub-module, the method comprising:

applying power initially to the ASIC device via the node with the low-power sub-module of the capless regulator module to initiate ASIC device power-up; and

detecting whether or not an external capacitance is coupled to the node.

13. The method of claim 12, further comprising:

subsequently applying power to the ASIC device via the node with the high-power sub-module of the capless regulator module in response to detection of the external capacitance coupled to the node.

14. The method of claim 12, further comprising:

subsequently applying power to the ASIC device via the node with the low-power sub-module of the capless regulator module in response to detection of the absence of an external capacitance coupled to the node.

15. The method of claim 13, further comprising:

completing the power-up of the ASIC device.

16. The method of claim 14, further comprising:

completing the power-up of the ASIC device.

17. The method of claim 15, further comprising:

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device after power-up.

18. The method of claim 16, further comprising:

selecting one of the linear regulator module and the capless regulator module to provide power to the ASIC device after power-up.

19. The method of claim 17, wherein the selecting is carried out by executing control logic in the ASIC device.

20. The method of claim 18, wherein the selecting is carried out by executing control logic in the ASIC device.

21. The method of clam 17, wherein the selecting is responsive to a stored state of a configuration register accessible by the ASIC device.

22. The method of clam 18, wherein the selecting is responsive to a stored state of a configuration register accessible by the ASIC device.