Semiconductor Memory Devices that are Configured to Analyze Read Failures and Related Methods of Operating Such Devices

• US 20090164871A1
• Filed: 11/21/2008
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jo, Sung-Kyu
• Granted Patent: US 8,839,071 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.

Claims

1. A semiconductor memory device comprising:

a nonvolatile memory that includes a plurality of memory cells; and

a memory controller that is configured to control at least some of the operations of the nonvolatile memory, the memory controller including an error correction unit;

wherein the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit.

2. The semiconductor memory device as set forth in claim 1, wherein the memory controller is further configured to increase a selective read voltage and perform a second read operation on the first of the plurality of memory cells if the output of the error correction unit indicates that the first of the plurality of memory cells was programmed with data “

1”

but was sensed as storing data “

0.”

3. The semiconductor memory device as set forth in claim 1 wherein the memory controller is further configured to determine if the read failure is due to soft-programming by increasing a selective read voltage and performing a second read operation on the first of the plurality of memory cells.

4. The semiconductor memory device as set forth in claim 3, wherein the memory controller is further configured to identify the read failure as being caused by soft-programming when a second read failure does not occur during the second read operation, and is also configured to identify the read failure as being caused by over-programming when the second read failure occurs during the second read operation.

5. The semiconductor memory device as set forth in claim 4, wherein the memory controller is further configured to repair the first of the plurality of memory cells by a charge refresh operation when the read failure is identified as being caused by soft-programming.

6. The semiconductor memory device as set forth in claim 4, wherein the memory controller is further configured to repair the first of the plurality of memory cells by increasing a de-selective read voltage when the read failure is identified as being caused by over-programming.

7. The semiconductor memory device as set forth in claim 1, wherein the memory controller is further configured to repair the first of the plurality of memory cells by a charge refresh operation when the read failure is identified as due to charge leakage.

8. The semiconductor memory device as set forth in claim 1, wherein the memory controller is further configured to repair the first of the plurality of memory cells by a charge refresh operation when the output of the error correction unit indicates that the first of the plurality of memory cells was programmed with data “

0”

but was sensed as storing data “

1.”

9. A method for analyzing a read failure of a semiconductor memory device that includes a nonvolatile memory and a memory controller, the method comprising:

analyzing an error correction code associated with a first data read operation from the nonvolatile memory to determine whether the read failure is due to charge leakage.

10. The method as set forth in claim 9, the method further comprising:

increasing a selective read voltage that was used in the first data read operation;

performing a second read operation using the increased selective read voltage to determine whether the read failure resulted because of soft-programming.

11. The method as set forth in claim 10, further comprising identifying the read failure as being caused by soft-programming if a second read failure does not occur during the second read operation.

12. The method as set forth in claim 10, further comprising identifying the read failure as being caused by over-programming if a second read failure occurs during the second read operation.

13. The method as set forth in claim 11, further comprising performing a charge refresh operation if the read failure is identified as being caused by soft-programming.

14. The method as set forth in claim 12, further comprising increasing a de-selective read voltage if the read failure is identified as being caused by over-programming.

15. The method as set forth in claim 9, further comprising performing a charge refresh operation if the read failure is identified as being caused by charge leakage.

16. A method of repairing a memory cell of a nonvolatile memory that experiences a read failure during a first read operation, the method comprising:

using an output of an error correction unit to classify the cause of the read failure, and

selecting a method for repairing the memory cell based on the classification of the cause of the read failure.

17. The method of claim 16, wherein the cause of the read failure is classified as being due to charge leakage if the output of the error correction unit indicates that the memory cell was programmed with data “

0”

but was sensed as storing data “

1”

.

18. The method of claim 16, wherein the cause of the read failure is classified as being one of soft-programming or over-programming if the output of the error correction unit indicates that the memory cell was programmed with data “

1”

but was sensed as storing data “

0.”

19. The method of claim 18, further comprising:

performing a second read operation on the memory cell after classifying the cause of the read failure being one of soft-programming or over-programming, wherein the second read operation is performed using a second selective read voltage that is different than a first selective read voltage that was used during the first read operation;

further classifying the cause of the read failure as being due to soft-programming if the output of the error correction unit indicates that a read failure did not occur on the memory cell during the second read operation and otherwise classifying the cause of the read failure as being due to over-programming; and

wherein selecting a method for repairing the memory cell based on the classification of the cause of the read failure comprises selecting a charge refresh operation if the cause of the read failure is classified as being due to soft-programming and selecting increasing a de-selective read voltage if the cause of the read failure is classified as being due to over-programming.

20. The method as set forth in claim 16, wherein the selected method for repairing the memory cell comprises performing a charge refresh operation when the read failure is classified as being caused by charge leakage.