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RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY

  • US 20090166621A1
  • Filed: 03/06/2009
  • Published: 07/02/2009
  • Est. Priority Date: 03/23/2007
  • Status: Active Grant
First Claim
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1. A wafer of semiconductor field effect transistors comprising:

  • one or more test structures forming a bridge circuit;

    a layer of dielectric material including one or more portions that cover one or more corresponding portions of the test structures; and

    one or more metal contacts configured to electrically connect the test structures through contact holes opened through the dielectric material covering the test structures.

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