SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090166677A1
• Filed: 12/08/2008
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: SHIBATA, Daisuke, Yanagihara, Manabu, Morita, Tatsuo, Uemoto, Yasuhiro
• Application Number:
  US12/329,939
• Publication Number:
  US 20090166677A1
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and

a transistor formed over the semiconductor substrate, wherein

the transistor includes a semiconductor layer laminate including a first nitride semiconductor layer and a second nitride semiconductor layer that are formed sequentially from the semiconductor substrate side, the second nitride semiconductor layer has a wider bandgap than that of the first nitride semiconductor layer, the transistor further includes a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode, the source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode.

2. The semiconductor device according to claim 1, wherein the cathode is an n-type region formed on the first surface side of the semiconductor substrate, and the anode is a p-type region formed on the second surface side of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the p-type region is formed at a distance from a side edge portion of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the cathode is an n-type region formed on the first surface side of the semiconductor substrate, and the anode is a Schottky electrode formed on the second surface side of the semiconductor substrate.

5. The semiconductor device according to claim 4, wherein the transistor is formed on the first surface and the Schottky electrode is a back electrode.

6. The semiconductor device according to claim 1, wherein the cathode is an n-type region formed on the first surface side of the semiconductor substrate, and the anode is formed by a Schottky electrode formed on the second surface side of the semiconductor substrate and a plurality of p-type regions formed spaced apart from each other on the second surface side of the semiconductor substrate.

7. The semiconductor device according to claim 1, further comprising a back electrode formed on the second surface of the semiconductor substrate, wherein the transistor is formed over the first surface of the semiconductor substrate.

8. The semiconductor device according to claim 1, further comprising a back electrode formed on the first surface of the semiconductor substrate, wherein the transistor is formed over the second surface of the semiconductor substrate.

9. The semiconductor device according to claim 1, further comprising a diffusion prevention layer formed on the first surface of the semiconductor substrate for preventing diffusion of a group-III element contained in the semiconductor layer laminate, wherein the cathode is an n-type region formed below the diffusion prevention layer.

10. The semiconductor device according to claim 1, further comprising:

a drain via plug connecting the drain electrode and the cathode to each other; and

a source via plug connecting the source electrode and the anode to each other.

11. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon, silicon carbide, or gallium nitride.

13. The semiconductor device according to claim 1, further comprising a second p-type semiconductor layer formed between the gate electrode and the semiconductor layer laminate.

12. A semiconductor device, comprising:

a semiconductor layer laminate including a first nitride semiconductor layer formed over a substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than that of the first nitride semiconductor layer;

a cathode electrode, a source electrode, and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate;

a gate electrode formed between the source electrode and the drain electrode;

a first p-type semiconductor layer formed between the cathode electrode and the source electrode; and

an anode electrode formed on the first p-type semiconductor layer, wherein

the source electrode and the anode electrode are electrically connected to each other, and

the drain electrode and the cathode electrode are electrically connected to each other.

14. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor substrate having on a first surface side thereof an n-type region that will serve as a cathode of a diode, and having a diffusion prevention layer between the n-type region and the first surface;

(b) forming an anode of the diode on a second surface side of the semiconductor substrate;

(c) forming over the first surface of the semiconductor substrate a nitride transistor having a channel region in which electrons travel in a direction parallel to the first surface and having a source electrode, a drain electrode, and a gate electrode; and

(d) forming a drain via plug electrically connecting the drain electrode and the n-type region to each other; and

(e) electrically connecting the source electrode and the anode to each other.

15. The method according to claim 14, wherein the step (a) includes the steps of (a1) forming the n-type region by implanting n-type impurities to the first surface side of the semiconductor substrate, and (a2) forming a diffusion prevention layer made of an oxide film in an upper portion of the n-type region by first implanting oxygen ions in the upper portion of the n-type region and then performing heat treatment.

16. The method according to claim 14, wherein the step (a) includes the steps of (a1) forming the n-type region by implanting n-type impurities to a first surface side of a lower substrate, (a2) forming a first oxide film on the first surface of the lower substrate after the step (a1), (a3) forming a second oxide film on a first surface side of an upper substrate, and (a4) forming the diffusion prevention layer by bonding the first oxide film and the second oxide film to each other.

17. The method according to claim 14, wherein the step (b) is a step of forming the anode by implanting p-type impurities to the second surface side of the semiconductor substrate.

18. The method according to claim 17, wherein the anode is formed before formation of the impurity diffusion layer.

19. The method according to claim 14, wherein the step (b) is a step of forming a Schottky electrode on the second surface side of the semiconductor substrate.

20. The method according to claim 14, wherein the step (e) is the step of forming a source via plug electrically connecting the source electrode and the anode to each other.