PHOTOGATE CMOS PIXEL FOR 3D CAMERAS HAVING REDUCED INTRA-PIXEL CROSS TALK

• US 20090166684A1
• Filed: 12/29/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Abandoned Application

• Current Assignee: Microsoft International Holdings BV (Microsoft Corporation)
• Original Assignee: 3DV Systems Ltd. (Microsoft Corporation)
• Inventors: Reiner, Thomas, Yahav, Giora
• Application Number:
  US12/344,601
• Publication Number:
  US 20090166684A1
• Time in Patent Office: Days
• US Class Current: 257/225
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type

Abstract

A CMOS photodetector pixel formed of a substrate, an epitaxial layer above the substrate including a first region having the same polarity but a lower impurity concentration as that of the substrate, and a gate arrangement including a first gate that forms a charge accumulation region in the epitaxial layer when the gate is energized, wherein the charge accumulation region extends deeper toward the substrate than in conventional constructions. The epitaxial layer includes a shielding structure for absorbing electrons generated therein by photons impinging on the pixel, except electrons generated close to the charge accumulation region. The shielding structure may have opposite polarity from that of the substrate, including a first portion under the first gate, and a second portion extending upward from the first portion at the margin of the pixel. Alternatively, the shielding structure may have the same polarity as the substrate, but a lower impurity concentration.

Claims

1. A CMOS photodetector pixel comprising:

a substrate having first polarity and impurity concentration;

an epitaxial layer formed above the substrate including a first region having the same polarity but a lower impurity concentration from that of the substrate;

an oxide layer formed above the epitaxial layer; and

a gate arrangement formed on the oxide layer including a first gate,

wherein the epitaxial layer includes a shielding structure having a polarity, impurity concentration and geometry such that it functions to substantially absorb electrons generated in the epitaxial layer by photons impinging on the pixel, except for electrons generated in close enough proximity to the first gate as to be attracted by an electric field generated when the first gate is electrically energized.

2. A CMOS photodetector pixel according to claim 1, wherein the first and second diffusions are embedded within respective wells within the epitaxial layer, the wells having the same polarity as the substrate.

3. A CMOS photodetector pixel as according to claim 1 wherein the shielding structure of the epitaxial layer comprises:

a first portion located above the substrate having opposite polarity from that of the substrate; and

a second portion having the same polarity as the first portion that extends upward from the first portion and defines the margin of the pixel.

4. A CMOS photodetector pixel according to claim 1 wherein the first gate is operable when suitably electrically biased to create a charge accumulation region in the first region of the epitaxial layer;

wherein the gate arrangement further includes second and third gates respectively spaced laterally from the first gate; and

further including;

first and second floating essentially capacitive diffusions within the epitaxial layer respectively on opposite sides of the second and third gates from the first gate, the second and third gates being operable when suitably electrically biased to provide charge flow paths between the charge accumulation region and the respective first and second floating diffusions;

the shielding structure of the epitaxial layer being operative to substantially prevent electrons generated in the epitaxial layer by photons impinging on the pixel from reaching the and first and second floating diffusions except through the charge flow paths from the charge accumulation region.

5. A CMOS photodetector pixel according to claim 3 wherein the first region of the epitaxial layer includes a part located below the first gate in which the impurity concentration is lowered after fabrication.

6. A CMOS photodetector pixel according to claim 3 wherein the first region of the epitaxial layer includes a part located below the first gate in which the impurity concentration is lowered by counter-doping after fabrication to a value of approximately 1e14 cm⁻

3.

7. A CMOS photodetector pixel according to claim 3 wherein the first region of the epitaxial layer is comprised of material grown on the substrate with an impurity concentration of about 1e 14 cm⁻

3.

8. A CMOS photodetector according to claim 3 wherein the center of the first portion of the shielding structure is located approximately 2 μ

m below the oxide layer.

9. A CMOS photodetector according to claim 3 wherein the center of the first portion of the shielding structure is located approximately in the range of about 1.5 to about 3.0 μ

m below the oxide layer.

10. A CMOS photodetector according to claim 3 wherein the thickness of the first portion of the shielding structure is in the range of about 0.4 to about 1.5 μ

m.

11. A CMOS photodetector according to claim 3 wherein the thickness of the first portion of the shielding structure is about 0.8 μ

m.

12. A CMOS photodetector according to claim 1 wherein the thickness of the epitaxial layer is in the range of about 5.0 to about 10.0 μ

m.

13. A CMOS photodetector according to claim 4 wherein the depth of the charge accumulation region in the epitaxial layer is in the range of about 1.5 to about 2.0 μ

m.

14. A CMOS photodetector according to claim 1 wherein the shielding structure is comprised substantially entirely of material having the same polarity as the substrate, but having a lower impurity concentration than that of the substrate.

15. A CMOS photodetector according to claim 1 wherein the thickness of the epitaxial layer between the substrate and the oxide layer is in the range of about 2.5 to about 4.0 μ

m.

16. A CMOS photodetector according to claim 1 wherein the thickness of the epitaxial layer between the substrate and the oxide layer is about 3.0 μ

m.

17. A CMOS photodetector according to claim 1 wherein the impurity concentration of the shielding structure is about 1e15 cm⁻

3.

18. A CMOS photodetector according to claim 1 wherein a charge accumulation region is formed in the epitaxial layer when the first gate is energized, and which extends downward from the oxide layer toward the substrate a distance in the range of about 1.5 to about 2.0 μ

m.

19. A CMOS photodetector pixel according to claim 14 , wherein the first gate is operable when suitably electrically biased to create a charge accumulation region in the first region of the epitaxial layer;

wherein the gate arrangement further includes second and third gates respectively spaced laterally from the first gate;

and further including;

first and second floating essentially capacitive diffusions within the epitaxial layer respectively on opposite sides of the second and third gates from the first gate, the second and third gates being operable when suitably electrically biased to provide charge flow paths between the charge accumulation region and the respective first and second floating diffusions;

the shielding structure of the epitaxial layer being operative to substantially prevent electrons generated in the epitaxial layer by photons impinging on the pixel from reaching the and first and second floating diffusions except through the charge flow paths from the charge accumulation region.

20. A photodetector comprising pixels formed in a semiconductor substrate, each pixel comprising:

a photogate for controlling a depletion region in the substrate under the photogate;

diffusion regions on either side of the depletion region;

gates on either side of the photogate for controlling electric fields between the depletion region and the diffusion regions; and

a substantially electrically conductive boundary region in the substrate that contains the depletion and diffusion regions.