Nonvolatile semiconductor memory with erase gate and its manufacturing method

• US 20090166708A1
• Filed: 12/19/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Io, Eiji
• Granted Patent: US 8,058,680 B2
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a select gate formed above the semiconductor substrate;

a floating gate formed above the semiconductor substrate; and

an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein the floating gate is formed at a position corresponding to a lateral side of the select gate.

3. The nonvolatile semiconductor memory device according to claim 1,

wherein at least a portion of the erase gate is formed lower than the surface of the semiconductor substrate.

4. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a device isolation structure formed on the semiconductor substrate,

wherein at least a portion of the erase gate is embedded within the device isolation structure.

5. The nonvolatile semiconductor memory device according to claim 1,

wherein the erase gate includes a cavity opposite the edge of the lower surface of the floating gate.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a device isolation structure formed to protrude from the surface of the semiconductor substrate;

a trench formed within the device isolation structure; and

a tunnel insulation film formed on an inner wall of the trench,

wherein the erase gate is formed above the tunnel insulation film so as to be embedded within the trench.

7. The nonvolatile semiconductor memory device according to claim 6,

wherein the floating gate includes:

a lower section enclosed between an adjoining device isolation structure; and

an upper section formed on the lower section, and overlapping a portion of the device isolation structure, and

wherein the erase gate is opposite an edge of a lower surface of the upper section via the tunnel insulation film.

8. The nonvolatile semiconductor memory device according to claim 7,

wherein the erase gate contains a cavity opposite the edge of the lower surface of the upper section.

9. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a program gate formed, via an insulation layer, above the floating gate.

10. The nonvolatile semiconductor memory device according to claim 9, further comprising:

a silicide film formed above an upper surface of the program gate.

11. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a gate insulation film formed above a channel region of a surface of the semiconductor substrate;

a first diffusion region and a second diffusion region formed on the semiconductor substrate so as to enclose the channel region;

a plug coupled to the first diffusion region;

a first silicide film formed above an upper surface of the plug; and

a second silicide film formed above a surface of the second diffusion region.

12. The nonvolatile semiconductor memory device according to claim 1,

wherein electrons within the floating gate are extracted to the erase gate by a Fowler-Nordheim (FN) tunneling method.

13. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a select gate formed above the semiconductor substrate;

a floating gate formed above the semiconductor substrate to a side of the select gate;

a device isolation structure formed on the semiconductor substrate; and

an erase gate formed on the device isolation structure,

wherein the erase gate is positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

14. The nonvolatile semiconductor memory device according to claim 13, further comprising:

a program gate formed above the floating gate;

a first diffusion region formed on the semiconductor substrate at a position adjacent to the floating gate;

a second diffusion region formed on the semiconductor substrate at a position adjacent to the select gate;

a plug formed above the first diffusion region, and coupled to the first diffusion region;

a first silicide film formed on an upper surface of the program gate;

a second silicide film formed on a surface of the plug;

a third silicide film formed on a surface of the select gate; and

a fourth silicide film formed on a surface of the second diffusion region.

15. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate; and

a memory cell array with a plurality of memory cells formed on the semiconductor substrate,

wherein each of the plurality of memory cells includes;

a select gate formed above the semiconductor substrate;

a floating gate formed above the semiconductor substrate; and

an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate, and

wherein the erase gate is jointly formed with a specified number of memory cells arrayed along a predetermined direction among the plurality of memory cells.

16. The nonvolatile semiconductor memory device according to claim 15,

wherein, in each of the plurality of memory cells, the floating gate is formed at a position corresponding to a lateral side of the select gate.

17. The nonvolatile semiconductor memory device according to claim 15, further comprising:

device isolation structures formed on the semiconductor substrate so as to extend in the predetermined direction,

wherein at least a portion of the erase gate is embedded within the device isolation structures.

18. The nonvolatile semiconductor memory device according to claim 15,

wherein the predetermined direction comprises a first direction, and

wherein the select gate is formed to extend in a second direction intersecting the first direction.

19. The nonvolatile semiconductor memory device according to claim 15,

wherein the memory cells positioned on an end of a specified number of memory cells comprise dummy cells, and

wherein the erase gates formed jointly with the specified number of memory cells are coupled to the select gates of the dummy cells corresponding to the specified memory cells.

20. The nonvolatile semiconductor memory device according to claim 15,

wherein each of the plurality of memory cells further includes:

a first diffusion region formed on the semiconductor substrate at a position adjacent to the floating gate;

a second diffusion region formed on the semiconductor substrate at a position adjacent to the select gate; and

a plug formed above the first diffusion region, and coupled to the first diffusion region.

21. The nonvolatile semiconductor memory device according to claim 19,

wherein adjacent memory cells arrayed along the predetermined direction share the plug and the first diffusion region, and

wherein the floating gate, the select gate and the second diffusion region of the respective adjacent memory cells arrayed along the predetermined direction are formed symmetrically with respect to the plug and the first diffusion region.

22. The nonvolatile semiconductor memory device according to claim 19,

wherein adjacent memory cells along the predetermined direction share the second diffusion region, and

wherein the floating gate, select gate, the plug and the first diffusion region of the respective adjacent memory cells arrayed along the predetermined direction are formed symmetrically with respect to the second diffusion region.