SEMICONDUCTOR DEVICE, METHOD FOR OPERATING A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20090166720A1
• Filed: 12/26/2007
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus
• Granted Patent: US 8,274,109 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

at least a pn-junction arranged in the semiconductor substrate;

at least a field electrode arranged at least next to a portion of the pn-junction, the field electrode being insulated from the semiconductor substrate; and

a switching device being electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

2. The semiconductor device of claim 1, wherein the pn-junction comprises a breakdown-susceptible region, and wherein the field electrode is arranged at least next to the breakdown-susceptible region of the pn-junction.

3. The semiconductor device of claim 1, wherein the switching device comprises a control terminal for controlling the switching device.

4. The semiconductor device of claim 1, further comprising a doping region arranged in the semiconductor substrate, the doping region forming the pn-junction with an adjacent region in the semiconductor substrate, and further comprising a contact pad in electrical connection with the doping region, and a control contact pad in electrical connection with the field electrode.

5. The semiconductor device of claim 1, further comprising a source region, a body region and a drift region, the body and drift regions forming the pn-junction, further comprising a gate electrode arranged next to the body region.

6. The semiconductor device of claim 1, further comprising a trench formed in the semiconductor substrate, wherein the field electrode is arranged in the trench.

7. A semiconductor device, comprising:

a semiconductor substrate comprising a first surface and a second surface arranged opposite to the first surface;

a first doping region formed in the semiconductor substrate at the first surface;

a second doping region formed in the semiconductor substrate at the second surface;

at least a first trench formed in the semiconductor substrate and extending from the first surface into the semiconductor substrate, the first trench comprising a gate electrode and a field electrode;

at least a second trench formed in the semiconductor substrate and extending from the first surface into the semiconductor substrate, the second trench being laterally spaced to the first trench and comprising at least a field electrode; and

a switching device being electrically connected to the field electrode of the second trench and adapted to apply selectively and dynamically one of a first electrical potential, which substantially corresponds to the electrical potential of the first doping region, and a second electrical potential, which substantially corresponds to the electrical potential of the second doping region, to the field electrode of the second electrode.

8. The semiconductor device of claim 7, wherein the switching device is adapted to connect selectively the field electrode of the second trench with one of the first and the second doping regions.

9. The semiconductor device of claim 7, wherein the field electrode of the first trench is electrically connected to the first doping region.

10. The semiconductor device of claim 7, wherein the semiconductor device comprises a control contact pad which is in electrical connection with the field electrode of the second trench, wherein the switching device is electrically connected to the control contact pad.

11. The semiconductor device of claim 7, wherein the second trench further comprises a gate electrode and each of the first and second trenches comprises a gate insulating layer for electrically insulating the respective gate electrodes from the semiconductor substrate.

12. The semiconductor device of claim 11, wherein the gate insulating layer of the second trench is thicker than the gate insulating layer of the first trench.

13. The semiconductor device of claim 7, further comprising a third doping region in contact with the first doping region, the third doping region being of opposite conductivity type to the first doping region.

14. The semiconductor device of claim 13, wherein a contact region is formed in the semiconductor substrate between adjacent trenches for providing an electrical connection to the third doping region.

15. The semiconductor device of claim 14, wherein the field electrode of the second trench comprises an upper edge which faces the first surface and which is arranged above a lower end of the contact region.

16. A semiconductor device, comprising:

a semiconductor substrate comprising a first surface and a second surface arranged opposite to the first surface;

a first doping region formed in the semiconductor substrate at the first surface;

a second doping region formed in the semiconductor substrate at the second surface;

at least a first trench formed in the semiconductor substrate and extending from the first surface into the semiconductor substrate, the first trench comprising at least a gate electrode;

at least a second trench formed in the semiconductor substrate and extending from the first surface into the semiconductor substrate, the second trench being laterally spaced to the first trench and comprising at least a field electrode;

a contact pad in electrical connection with the first doping region; and

a control contact pad in electrical connection with the field electrode of the second trench.

17. The semiconductor device of claim 16, further comprising a switching device adapted to selectively connect the field electrode of the second trench with one of the first and the second doping regions, wherein the switching device is electrically connected to the control contact pad.

18. A method for operating a semiconductor device, comprising:

providing a semiconductor device which comprises a semiconductor substrate comprising at least a pn-junction arranged in the semiconductor substrate, at least a field electrode arranged at least next to a portion of the pn-junction, the field electrode being insulated from the semiconductor substrate;

operating the pn-j unction at least temporarily in reverse mode;

applying a first electrical potential to the field electrode; and

temporarily disconnecting the field electrode from the first electrical potential and applying a second electrical potential to the field electrode so that the avalanche breakdown characteristics of the pn-junction are altered.

19. The method of claim 18, wherein the second electrical potential is repeatedly temporarily applied to the field electrode.

20. The method of claim 18, wherein the second electrical potential is applied to the field electrode shortly before an avalanche breakdown occurs.

21. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming at least a pn-junction in the semiconductor substrate;

forming at least a field electrode arranged at least next to a portion of the pn-junction, the field electrode being insulated from the semiconductor substrate; and

forming a switching device in electrical connection to the field electrode.

22. The method of claim 21, wherein the semiconductor substrate comprises a first surface and a second surface arranged opposite to the first surface, the method further comprising:

forming at least a first and a second trench in the semiconductor substrate at the first surface in spaced relation to each other;

forming at least respective field electrodes in the first and second trenches; and

forming a first doping region in the semiconductor substrate at the first surface, a second doping region in the semiconductor substrate at the second surface, and a third doping region in contact with the first doping region and between the first and second doping regions, the third doping region being of opposite conductivity type to the first doping region and adjoining the pn-junction.

23. The method of claim 22, further comprising:

forming a contact region in the semiconductor substrate between adjacent trenches for providing an electrical connection to the third doping region; and

forming the field electrode of the second trench such that it comprises an upper edge which is arranged above a lower end of the contact region.

24. The method of claim 22, wherein each of the first and second trenches are formed such that they comprise a gate insulating layer for electrically insulating the respective gate electrodes from the semiconductor substrate, wherein the gate insulating layer of the second trench is formed to be at least partially thicker than the gate insulating layer of the first trench.

25. The method of claim 21, further comprising forming a control contact pad which is electrically connected to the field electrode.