Structure and Method for Forming Shielded Gate Trench FET with Multiple Channels

• US 20090166728A1
• Filed: 12/26/2007
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James
• Granted Patent: US 7,772,668 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

Claims

1. A field effect transistor (FET) comprising:

a pair of trenches extending into a semiconductor region;

a first shield electrode in a lower portion of each trench;

a gate electrode in an upper portion of each trench over but insulated from the shield electrode by an inter-electrode dielectric; and

first and second well regions of a first conductivity type laterally extending in the semiconductor region between the pair of trenches, the first and second well regions abutting sidewalls of the pair of trenches, the first and second well regions being vertically spaced from one another by a first drift region of a second conductivity type,

wherein the gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

2. The FET of claim 1 wherein when the FET is biased in the on state, two separate channels are formed along portions of each trench sidewall where the first and second well regions abut.

3. The FET of claim 1 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second well region is laterally directly next to the first shield electrode in each trench.

4. The FET of claim 1 further comprising:

a shield dielectric lining lower sidewalls and bottom of each trench;

a gate dielectric lining upper sidewalls of each trench;

source regions of the second conductivity type flanking upper sidewalls of each trench; and

a heavy body region of the first conductivity type extending in the first well region.

5. The FET of claim 1 wherein the first well region is above the second well region, the FET further comprising a third well region of the first conductivity type laterally extending in the semiconductor region between the pair of trenches, the third well region abutting sidewalls of the pair of trenches, the third well region being vertically spaced from the second well region by a second drift region of the second conductivity type.

6. The FET of claim 5 wherein the gate and first shield electrodes are positioned relative to the first, second and third well regions such that a channel is formed in each of the first, second and third well regions when the FET is biased in the on state.

7. The FET of claim 5 wherein when the FET is biased in the on state, three separate channels are formed along portions of each trench sidewall where the first, second and third well regions abut.

8. The FET of claim 5 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second and third well regions are laterally directly next to the first shield electrode in each trench.

9. The FET of claim 1 wherein the first well region is above the second well region, the FET further comprising:

a third well region of the first conductivity type laterally extending in the semiconductor region between the pair of trenches, the third well region abutting sidewalls of the pair of trenches, the third well region being vertically spaced from the second well region by a second drift region of the second conductivity type; and

a second shield electrode in the trench below the first shield electrode, the first and second shield electrodes being insulated from one another.

10. The FET of claim 9 wherein the gate electrode, the first shield electrode and the second shield electrode are positioned relative to the first, second and third well regions such that a channel is formed in each of the first, second and third well regions when the FET is biased in the on state.

11. The FET of claim 9 wherein when the FET is biased in the on state, three separate channels are formed along portions of each trench sidewall where the first, second and third well regions abut.

12. The FET of claim 9 wherein the first well region is laterally directly next to the gate electrode in each trench, the second well region is laterally directly next to the first shield electrode in each trench, and the third well region is laterally directly next to the second shield electrode in each trench.

13. A field effect transistor (FET) comprising:

a stack of, from the top to bottom, a first well region of a first conductivity type, a first drift region of a second conductivity type, a second well region of the first conductivity type, and a second drift region of the second conductivity type, laterally extending between and abutting sidewalls of two trenches, each trench having a stack of, from the top to bottom, a gate electrode and a first shield electrode insulated from one another by an inter-electrode dielectric,

wherein the gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

14. The FET of claim 13 wherein when the FET is biased in the on state, two separate channels are formed along portions of each trench sidewall where the first and second well regions abut.

15. The FET of claim 13 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second well region is laterally directly next to the first shield electrode in each trench.

16. The FET of claim 13 further comprising:

a shield dielectric lining lower sidewalls and bottom of each trench;

a gate dielectric lining upper sidewalls of each trench;

source regions of the second conductivity type flanking upper sidewalls of each trench; and

a heavy body region of the first conductivity type extending in the first well region.

17. The FET of claim 13 further comprising a third well region of the first conductivity type laterally extending between and abutting the two trenches, the third well region extending below the second drift region.

18. The FET of claim 17 wherein when the FET is biased in the on state, three separate channels are formed along portions of each trench sidewall where the first, second and third well regions abut.

19. The FET of claim 17 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second and third well regions are laterally directly next to the first shield electrode in each trench.

20. The FET of claim 13 further comprising:

a third well region of the first conductivity type laterally extending between and abutting the two trenches, the third well region extending below the second drift region; and

a second shield electrode in the trench below the first shield electrode, the first and second shield electrodes being insulated from one another.

21. The FET of claim 20 wherein when the FET is biased in the on state, three separate channels are formed along portions of each trench sidewall where the first, second and third well regions abut.

22. The FET of claim 20 wherein the first well region is laterally directly next to the gate electrode in each trench, the second well region is laterally directly next to the first shield electrode in each trench, and the third well region is laterally directly next to the second shield electrode in each trench.

23. A method of forming a field effect transistor (FET), the method comprising:

forming a pair of trenches extending into a semiconductor region of a first conductivity type;

forming a shield electrode in a lower portion of each trench;

forming a gate electrode in an upper portion of each trench over but insulated from the shield electrode; and

forming first and second well regions of a second conductivity type in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches,

wherein the gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

24. The method of claim 23 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second well region is laterally directly next to the first shield electrode in each trench.

25. The method of claim 23 further comprising:

forming a shield dielectric lining lower sidewalls and bottom of each trench;

forming a gate dielectric lining upper sidewalls of each trench;

forming source regions of the second conductivity type flanking upper sidewalls of each trench; and

forming a heavy body region of the first conductivity type extending in the first well region.

26. The method of claim 23 wherein the first well region extends over the second well region, and the first region is formed before the second well region.

27. The method of claim 26 wherein the first well region extends over the second well region, the method further comprising:

forming a third well region of the first conductivity type in the semiconductor region between the pair of trenches, the third well region abutting sidewalls of the pair of trenches, the third well region being vertically spaced from the second well region.

28. The method of claim 27 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second and third well regions are laterally directly next to the first shield electrode in each trench.