TRENCH GATE MOSFET AND METHOD FOR FABRICATING THE SAME

• US 20090166734A1
• Filed: 12/28/2008
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Kim, Hee-Dae
• Granted Patent: US 7,851,300 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench gate MOSFET and a fabrication method thereof includes forming a first epitaxial layer over a semiconductor substrate, and then forming a second epitaxial layer formed over the first epitaxial layer, and then forming a body region over the second conductive type second epitaxial layer, and then forming a circular cross-section in a portion of the body region by performing an ion implantation process on the body region such that a bottom area thereof has a circular cross-section.

Claims

1. A device comprising:

a first conductive type semiconductor substrate;

a second conductive type first epitaxial layer formed over the first conductive type semiconductor substrate;

a second conductive type second epitaxial layer formed over the second conductive type first epitaxial layer;

a first conductive type body region formed over the second conductive type second epitaxial layer;

a plurality of trenches formed spaced apart in the first conductive type body region;

a gate buried in each one of the trenches;

a plurality of second conductive type emitter regions formed in the first conductive type body region; and

a contact hole formed in the first conductive type body region between adjacent second conductive type emitter regions,

wherein a bottom portion of the first conductive type body region formed under the contact hole and contacting the second conductive type second epitaxial layer has a circular cross-section.

2. The device of claim 1, further comprising a gate oxide layer formed over the surface of each one of the trench under the gate.

3. The device of claim 1, wherein the first conductive type body region between the bottom area of the contact hole and the second conductive type second epitaxial layer maintains a predetermined thickness.

4. The device of claim 1, wherein the device comprises a trench gate MOSFET.

5. A method comprising:

sequentuially forming a second conductive type first epitaxial layer and a second conductive type second epitaxial layer over a first conductive type semiconductor substrate; and

then

forming a first conductive type body region over the second conductive type second epitaxial layer; and

then

injecting first conductive type impurities in the first conductive type body region in order that a bottom area thereof has a circular cross-section; and

then

forming a plurality of trenches spaced apart in the first conductive body region; and

then

forming a gate in a respective one of the trenches; and

then

forming second conductive type emitter regions in the first conductive type body region; and

then

forming a contact hole at the upper surface of the first conductive type body region between adjacent ones of the second conductive type emitter regions.

6. The method of claim 5, further comprising, before forming the gate:

forming a gate oxide layer in a respective one of the trenches.

7. The method of claim 5, wherein the first conductive type body region between the bottom area of the contact hole and the second conductive type second epitaxial layer is formed to maintain a predetermined thickness.

8. The method of claim 5, further comprising, after forming the plurality of trenches and before forming the gate:

etching the walls the trenches.

9. The method of claim 5, further comprising, after etching the walls of the trenches:

forming a sacrificial oxide layer over the walls of the trench.

10. The method of claim 5, wherein the bottom area of the first conductive type body region corresponds spatially to the bottom area of the contact hole.

11. A method comprising:

forming a first epitaxial layer over a semiconductor substrate; and

then

forming a second epitaxial layer formed over the first epitaxial layer; and

then

forming a body region over the second conductive type second epitaxial layer; and

then

forming a circular cross-section in a portion of the body region by performing an ion implantation process on the body region such that a bottom area thereof has a circular cross-section; and

then

forming gate structures spaced apart extending through the body region and partially in the second epitaxial layer; and

then

forming emitter regions in the first conductive type body region; and

then

forming a contact hole in the body region between the second conductive type emitter regions and above a portion of the body region having the circular cross-section.

12. The method of claim 11, wherein the first epitaxial layer comprises an N+ epitaxial layer.

13. The method of claim 12, wherein the second epitaxial layer comprises an N−

epitaxial layer.

14. The method of claim 13, wherein the semiconductor substrate comprises a highly concentrated P++semiconductor substrate.

15. The method of claim 11, wherein forming the body region comprises performing a second ion implantation process injecting P−

impurities into the body region.

16. The method of claim 15, wherein forming the circular cross-section in the portion of the body region comprises performing a second ion implantation process on the body region injecting P−

impurities into the portion of body region.

17. The method of claim 11, wherein the bottom area of the first conductive type body region corresponds spatially to the bottom area of the contact hole.

18. The method of claim 11, wherein forming the gate structure comprises:

forming a plurality of trenches spaced apart extending through the body region and partially in the second epitaxial layer; and

then

etching the walls the trenches; and

then

forming a sacrificial oxide layer over the walls of the trench; and

then

forming a gate oxide layer in a respective one of the trenches; and

then

forming a gate in a respective one of the trenches.

19. The method of claim 11, further comprising, after forming the contact hole:

forming an emitter electrode in the contact hole.

20. The method of 19, forming a collector electrode at the semiconductor substrate.