REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES

• US 20090166741A1
• Filed: 12/26/2007
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Kavalieros, Jack T., Doyle, Brian S., Pillarisetty, Ravi
• Granted Patent: US 8,030,163 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

Claims

1. A method comprising:

depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins;

forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins;

removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins;

depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film; and

etching the spacer gate dielectric to completely, or nearly completely, remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

2. A method according to claim 1 wherein patterning the sacrificial gate electrode results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more multi-gate fins that is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) and where s is the pre-determined spacer gate dielectric thickness:

g=f+2s.

3. A method according to claim 1 wherein a height of the sacrificial gate electrode is selected such that a height of the remaining spacer gate dielectric after etching the spacer gate dielectric is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching the spacer gate dielectric reduces the height of the remaining spacer gate dielectric.

4. A method according to claim 1 wherein forming a dielectric film comprises:

depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more multi-gate fins; and

polishing the oxide material back to the level of the sacrificial gate electrode.

5. A method according to claim 1 wherein depositing spacer gate dielectric to the gate region of the one or more multi-gate fins comprises conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto the sacrificial gate electrode material and not conformally growing spacer gate dielectric onto the final gate electrode material.

6. A method according to claim 1 wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins at any time during a gate formation process.

7. A method according to claim 1 wherein the one or more multi-gate fins comprise at least one tri-gate fin, the tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface wherein etching the spacer gate dielectric substantially removes the spacer gate dielectric from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area to be coupled with the final gate electrode.

8. A method according to claim 1 further comprising:

performing tip implantation prior to forming a dielectric film;

depositing the final gate electrode to the gate region of the one or more multi-gate fins such that the final gate electrode is coupled to the pre-determined thickness of spacer gate dielectric that remains after etching the spacer gate dielectric; and

removing the dielectric film such that the pre-determined thickness of spacer gate dielectric remains coupled to the deposited final gate electrode.

9. A method according to claim 1 wherein the one or more multi-gate fins each have a top surface, a first sidewall surface, and a second sidewall surface, the method further comprising:

epitaxially depositing a semiconductor material to the top surface, the first sidewall surface, and the second sidewall surface of the source and drain regions of the one or more multi-gate fins to reduce external resistance (R_ext) in a multi-gate transistor device.

10. An apparatus comprising:

a semiconductor substrate;

at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

epi-growth coupled to the source and drain regions of the multi-gate fin;

a gate electrode coupled with the gate region of the multi-gate fin; and

a spacer gate dielectric coupled to the gate electrode wherein substantially no spacer gate dielectric is disposed between the gate electrode and the multi-gate fin in the gate region.

11. An apparatus according to claim 10 wherein the multi-gate fin has a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface, the source and drain regions being substantially free of the spacer gate dielectric material on the top surface, the first sidewall surface, and the second sidewall surface.

12. An apparatus according to claim 11 wherein the source and drain regions of the multi-gate fin are not coupled directly to the spacer gate dielectric material at any time during a spacer gate dielectric formation process.

13. An apparatus according to claim 10 wherein the spacer gate dielectric is conformally grown along a sacrificial dielectric and not conformally grown along the gate electrode.

14. An apparatus according to claim 10 wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate electrode comprises polysilicon, and the spacer gate dielectric comprises a nitride material.

15. An apparatus according to claim 10 wherein the multi-gate fin comprises a tri-gate fin of a multi-gate transistor device, the tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface wherein the epi-growth is coupled to the top surface, the first sidewall surface, and the second sidewall surface in the source and drain regions to reduce external resistance (R_ext) in the multi-gate transistor device.