REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN

• US 20090166742A1
• Filed: 12/26/2007
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Kavalieros, Jack T., Rakshit, Titash, Doyle, Brian S., Pillarisetty, Ravi
• Granted Patent: US 7,763,943 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

Claims

1. An apparatus comprising:

a semiconductor substrate; and

one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the gate region of the one or more fins comprises a semiconductor material and wherein the source and drain regions of the one or more fins comprise a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

2. An apparatus according to claim 1 wherein the semiconductor substrate is coupled with the semiconductor portion of the source and drain regions of the one or more fins to reduce current leakage to the semiconductor substrate.

3. An apparatus according to claim 1 wherein the metal portion of the source and drain regions is disposed to reduce parasitic contact resistance in the multi-gate transistor device by increasing electrical conductivity in the source and drain regions.

4. An apparatus according to claim 1 wherein the metal portion is formed by a replacement process, the metal portion comprising aluminum, titanium, cobalt, gold, silver, platinum, nickel, alloys or combinations thereof.

5. An apparatus according to claim 1 further comprising a gate stack coupled with the gate region of the one or more fins wherein the gate stack comprises:

a gate dielectric film coupled with the one or more fins;

a first gate electrode comprising metal coupled with the gate dielectric film; and

a second gate electrode comprising polysilicon coupled with the first gate electrode.

6. An apparatus according to claim 1 wherein the semiconductor material and the semiconductor portion comprise silicon.

7. An apparatus according to claim 1 wherein the multi-gate transistor device is a tri-gate device having reduced external resistance (R_ext) in comparison to a tri-gate device having only the semiconductor material in the source and drain regions.

8. A method comprising:

preparing one or more multi-gate fins comprising semiconductor material for partial replacement with a metal, the one or more multi-gate fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;

removing a portion of the semiconductor material from the source and drain regions of the one or more multi-gate fins; and

replacing the removed semiconductor material with a metal to reduce parasitic contact resistance in a multi-gate transistor device by increasing electrical conductivity in the source and drain regions.

9. A method according to claim 8 wherein preparing one or more multi-gate fins comprises:

depositing a hardmask dielectric film to the source and drain regions of the one or more multi-gate fins;

polishing the hardmask dielectric film to a pre-determined thickness;

depositing a sacrificial dielectric to the gate region of the one or more multi-gate fins and to the hardmask dielectric film;

polishing the sacrificial dielectric back to the hardmask dielectric film such that the sacrificial dielectric remains coupled to the gate region and does not remain coupled to the hardmask dielectric film; and

etching the hardmask dielectric film to expose the semiconductor material of the one or more multi-gate fins in the source and drain regions.

10. A method according to claim 9 wherein depositing a hardmask dielectric film comprises depositing an oxide material and wherein depositing a sacrificial dielectric comprises depositing a nitride material.

11. A method according to claim 8 wherein removing a portion of the semiconductor material from the source and drain regions of the one or more multi-gate fins comprises:

etching out a portion of the semiconductor material from the source and drain regions wherein the semiconductor material of the gate region is protected from the etching by a sacrificial dielectric coupled with the gate region.

12. A method according to claim 8 wherein replacing the removed semiconductor material with a metal comprises depositing aluminum, titanium, cobalt, gold, silver, platinum, nickel, alloys or combinations thereof to replace the removed semiconductor material in the source and drain regions of the one or more multi-gate fins, wherein the one or more multi-gate fins comprise one or more tri-gate fins.

13. A method according to claim 8 wherein replacing the removed semiconductor material with a metal comprises:

depositing an electrically conductive metal film to replace the removed semiconductor material in the source and drain regions of the one or more multi-gate fins;

polishing the deposited metal film back to a sacrificial dielectric coupled with the gate region of the one or more multi-gate fins;

annealing the deposited metal and the remaining semiconductor material in the source and drain regions of the one or more multi-gate fins to decrease interfacial resistance between the deposited metal and the remaining semiconductor material; and

etching to recess the deposited metal back to a hardmask dielectric film coupled with the source and drain regions of the one or more multi-gate fins such that the deposited metal remains only in the source and drain regions of the one or more multi-gate fins.

14. A method according to claim 13 further comprising:

depositing additional dielectric material to the hardmask dielectric film;

polishing the additional dielectric material back to the level of the sacrificial dielectric; and

removing the sacrificial dielectric to allow for gate stack formation in the gate region.

15. A method according to claim 8 further comprising:

forming a multi-gate stack on the gate region of the one or more multi-gate fins wherein forming a multi-gate stack comprises;

depositing a gate dielectric material to the gate region of the one or more multi-gate fins;

depositing a first gate electrode comprising metal to the gate dielectric material; and

depositing a second gate electrode comprising polysilicon to the first gate electrode.