FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS

• US 20090166804A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Schrom, Gerhard, Paillet, Fabrice, Gardner, Donald S., Hazucha, Peter, Karnik, Tanay
• Granted Patent: US 7,867,787 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Claims

1. A method comprising:

forming a first layer of magnetic material in an opening in a first dielectric layer;

forming a barrier layer in a first via opening disposed in the first dielectric layer and then forming a conductive material on the barrier layer;

forming a second dielectric layer on the first magnetic layer;

forming at least one second via opening and at least one conductive structure opening in the second dielectric layer;

forming a barrier layer in the at least one second via opening and in the at least one conductive structure opening, and then forming a conductive material in the at least one second via opening and in the at least one conductive structure opening;

forming a third layer of dielectric material on the conductive material in the conductive structure opening;

forming an opening in the third dielectric layer; and

forming a second layer of magnetic material in the opening, wherein the first and second layers of the magnetic material are coupled to one another.

2. The method of claim 1 further comprising wherein the magnetic material comprises CoZrTa, CoNbTa, NiFe, CoP, COPB, CoPRe, CoZr, CoZr Mo, FeCoAlN, CoZrTaN, FeCoP, COPW, COPBW, FeTaN, FeCoBSi, FeCoZrO, FeCoHfO, FeCoTiO, CoTi, FeCoB, CoZrOx, NiCuZnFeOx and combinations thereof.

3. The method of claim 1 further comprising forming a first thin dielectric layer on the first magnetic material prior to forming the second dielectric layer, wherein the first thin dielectric layer comprises a thickness of about 0.1 microns to about 0.5 microns.

4. The method of claim 1 further comprising wherein the barrier layer comprises at least one of Ta, TaN, and wherein the conductive material comprises a copper containing material.

5. The method of claim 1 further comprising wherein at least one of the first, second and third dielectric layers comprise an ILD, and wherein the ILD comprises a thickness of less than about 3.5 microns.

6. The method of claim 1 further comprising wherein the first layer of magnetic material is disposed on a substrate, wherein the substrate comprises a package substrate comprising a multilevel metallization CMOS die.

7. The method of claim 1 further comprising forming a passivation layer on the second layer of magnetic material.

9. The method of claim 1 further comprising forming a seed layer prior to forming the magnetic material that is disposed beneath the magnetic material, wherein the seed layer is formed by at least one of a sputtering, reactive sputtering, evaporation, atomic layer deposition, chemical vapor deposition, electroplating and electroless plating technique.

8. The method of claim 8 further comprising forming a passivation opening in the passivation layer, and then forming a conductive bump in the passivation opening.

10. A method comprising:

filling a magnetic via with a via magnetic material, wherein the via magnetic material couples to a first layer of magnetic material disposed within a dielectric layer on a substrate; and

forming a second layer of magnetic material on the via magnetic material.

11. The method of claim 10 further comprising wherein the magnetic via is filled by using at least one of a sputtering, electroplating, reactive sputtering, evaporation, atomic layer deposition, chemical vapor deposition, electroplating, electroless plating and a CVD technique, followed by a CMP process, and wherein the via magnetic material is planarized with the dielectric layer.

12. The method of claim 10 further comprising wherein the via magnetic material comprises at least one of a highly resistive material and an insulating material, and wherein the via magnetic material is different in composition to the first layer and the second layer of the magnetic material.

13. A structure comprising:

a first layer of magnetic material and at least one via structure disposed in a first dielectric layer;

a second dielectric layer disposed on the first magnetic layer;

at least one conductive structure disposed in the second dielectric layer;

a third layer of dielectric material disposed on the conductive structure;

a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

14. The structure of claim 13 wherein the magnetic material comprises CoZrTa, CoNbTa, NiFe, CoP, COPB, CoPRe, CoZr, CoZr Mo, FeCoAlN, CoZrTaN, FeCoP, COPW, COPBW, FeTaN, FeCoBSi, FeCoZrO, FeCoHfO, FeCoTiO, CoTi, FeCoB, CoZrOx, NiCuZnFeOx and combinations thereof.

15. The structure of claim 13 further comprising a conductive bump coupled to the at least one via, wherein the conductive bump is disposed on a passivation layer disposed on the second layer of magnetic material.

16. The structure of claim 13 wherein the dielectric layer comprises an ILD, wherein the ILD comprises a thickness of less than about 3.5 microns.

17. The structure of claim 13 wherein a distance between a top surface of the conductive structure and a bottom surface of the second layer of magnetic material comprises below about 0.5 micron.

18. The structure of claim 13 wherein a seed layer is disposed beneath the first and second layers of magnetic material.

19. The structure of claim 13 wherein the structure comprises a portion of a package substrate comprising a multilevel metallization CMOS structure.

20. The structure of claim 13 wherein the structure comprises a portion of at least one of an on-chip and an on-package voltage converter, an RF high-frequency circuit, an EMI noise reduction circuit and radar circuitry.