PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS

• US 20090166846A1
• Filed: 12/28/2007
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirby, Kyle K., Pratt, David S., Ray, Dewali
• Granted Patent: US 8,084,854 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/043 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]

Abstract

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Claims

1. A system of stacked microelectronic dies, comprising:

a first microelectronic die including a substrate having a front side and a back side, a metal substrate pad at the front side, and a first integrated circuit electrically coupled to the substrate pad;

a pass-through 3D through-die interconnect that extends, at least, through the substrate between the front side and back side, the pass-through interconnect also extending through the substrate pad but being electrically isolated from the substrate pad; and

a second microelectronic die attached to the back side of the substrate and including a second integrated circuit electrically coupled to the pass-through interconnect at the back side of the substrate.

2. The system of claim 1 wherein the first die further includes a first metal bonding pad electrically coupled to the first integrated circuit via the substrate pad and a second metal bonding pad electrically coupled to the second integrated circuit via the pass-through interconnect.

3. The system of claim 1 wherein the first die further includes a dielectric layer and first and second metal traces are routed to a common surface area associated with the substrate pad, the first trace is connected to the substrate pad, the second trace is connected to the pass-through interconnect, and the dielectric layer electrically isolates the second trace from the substrate pad and/or the first trace.

4. The system of claim 1, further comprising an interposer substrate carrying the first and second dies, the interposer substrate including a first bond pad electrically coupled to the substrate pad and the first integrated circuit, and a second bond pad electrically coupled to the pass-through interconnect and the second integrated circuit.

5. The system of claim 1 wherein the first and/or second integrated circuits comprise at least one device selected from the group consisting of a processing device, a memory device, and an imager device, and wherein the pass-through interconnect is a component of an electrical communication path to the second integrated circuit that is electrically independent of the first integrated circuit.

6. A microelectronic workpiece, comprising:

a substrate including a semiconductor circuit, a metal contact pad positioned at a front side of the substrate and electrically coupled to the semiconductor circuit, and a hole having a sidewall that extends at least partially through the substrate and the metal pad;

a dielectric layer attached to a section of the sidewall of the hole that includes the metal pad and the substrate, the dielectric layer also extending over a front-side contact surface of the metal pad; and

a metal layer attached to at least a portion of the dielectric layer adjacent the sidewall of the hole and the front-side contact surface of the metal pad, the metal layer being electrically isolated from the substrate pad via the dielectric layer.

7. The workpiece of claim 6 wherein the dielectric layer is attached to the front-side contact surface of the metal pad.

8. The workpiece of claim 6, further comprising a metal trace positioned between a portion of the dielectric layer and a portion of the front-side contact surface of the metal pad.

9. The workpiece of claim 6 wherein the substrate includes a back-side contact positioned at a back side of the substrate and electrically coupled with the metal layer.

10. The workpiece of claim 6 wherein the metal layer comprises a first metal layer, the sidewall of the hole comprises a first sidewall, the dielectric layer comprises a first dielectric layer, and the front-side contact surface of the metal pad comprises a first front-side contact surface, and wherein the workpiece further comprises:

a second dielectric layer attached to a section of a second sidewall of the hole that includes the metal pad and the substrate; and

a second metal layer attached to at least a portion of the second dielectric layer adjacent the second sidewall of the hole and the second front-side contact surface of the metal pad, the second metal layer being electrically isolated from the first metal layer via the second dielectric layer;

wherein;

a) the second metal layer is electrically isolated from the substrate pad via the second dielectric layer;

or

b) the second metal layer is electrically coupled to the semiconductor circuit via a second front-side contact surface of the metal pad.

11. A semiconductor device, comprising:

a substrate having a front side and a back side and including an integrated circuit and metal substrate pads coupled to the integrated circuit and the front side of the substrate;

a redistribution layer at the front side of the substrate and including metal traces; and

through-die interconnects extending through individual substrate pads towards the back side of the substrate and being electrically coupled with individual traces;

wherein the interconnects and associated traces are electrically isolated from the integrated circuit.

12. The semiconductor device of claim 11 wherein a second portion of the interconnects and associated traces are electrically coupled with the integrated circuit.

13. The semiconductor device of claim 11 wherein the first portion of the interconnects and associated traces include a dielectric material interposed between the individual substrate pads and the individual traces or between the individual substrate pads and the individual interconnects.

14. A method of manufacturing a stacked system of microelectronic dies, the method comprising:

aligning a metal contact of a first microelectronic die with a pass-through 3D interconnect at a back side of a second microelectronic die, the pass-through interconnect being formed through a metal substrate pad at a front side of the second die and being electrically isolated from the substrate pad; and

coupling the metal contact of the first die with the pass-through interconnect.

15. The method of claim 14, further comprising forming a dielectric layer between the pass-through interconnect and a contact surface of the substrate pad of the second die.

16. The method of claim 14, further comprising forming a dielectric layer that lines a first portion of the pass-through interconnect extending through the second die and a second portion of the pass-through interconnect extending above a contact surface of the substrate pad of the second die.

17. The method of claim 14 wherein the substrate pad of the second die is electrically coupled with a first integrated circuit carried by the second die, and wherein the metal contact is electrically coupled with a second integrated circuit carried by the first die.

18. The method of claim 14, further comprising:

forming a first metal trace at the front side of the second die, the first trace being electrically coupled to the substrate pad of the second die; and

forming a second metal trace at the front side of the second die, the second trace being electrically coupled to the pass-through interconnect and electrically isolated from the first trace and the substrate pad of the second die.

19. The method of claim 14, further comprising coupling the second die to an interposer substrate by a process that includes:

connecting the substrate pad to a first bond pad of the interposer substrate; and

connecting the pass-through interconnect to a second bond pad of the interposer substrate.

20. A method of manufacturing a pass-through interconnect, the method comprising:

forming a hole in a semiconductor substrate, the hole including a sidewall that extends through a substrate pad positioned at a front-side surface of the substrate, the substrate pad being in electrical communication with an integrated circuit carried by the substrate;

at least partially lining a contact surface of the substrate pad and a section of the sidewall with a dielectric layer; and

forming a metal layer adjacent the dielectric layer and coupled with the contact surface of the substrate pad and the sidewall, the dielectric layer electrically isolating the metal layer from the substrate pad.

21. The method of claim 20 wherein the metal layer is attached to a surface of the dielectric layer, and wherein the method further comprises forming a metal trace at the front-side surface of the substrate, the metal trace being attached to a surface of the metal layer.

22. The method of claim 20 wherein forming the hole further comprises forming the hole through an insulating layer and metal trace of a redistribution layer attached to the substrate, wherein the trace lines a portion of the contact surface of the substrate pad, and wherein the dielectric layer is attached to a section of the trace adjacent the contact surface.

23. The method of claim 20 wherein at least partially lining the contact surface of the substrate pad and the section of the sidewall with the dielectric layer includes:

depositing the dielectric layer at the front-side surface of the substrate;

forming a mask that covers a portion of the hole and a portion of the substrate pad; and

removing unmasked portions of the dielectric layer from the front-side surface of the substrate.

24. The method of claim 20 wherein forming the metal layer includes:

depositing a seed layer at the front-side surface of the substrate;

forming a mask on top of a portion of the seed layer, the mask exposing a portion of the seed layer within the hole and adjacent a portion of the substrate pad; and

plating the exposed portion of the seed layer with the metal layer.

25. The method of claim 20 further comprising thinning the semiconductor substrate to expose a portion of the metal layer at a back-side surface of the substrate.