CIRCUIT SUBSTRATE, CIRCUIT DEVICE AND MANUFACTURING PROCESS THEREOF

• US 20090166895A1
• Filed: 12/23/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: NOGUCHI, Mitsuru, Takakusaki, Sadamichi
• Granted Patent: US 7,964,957 B2
• Time in Patent Office: Days
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/05 Insulated conductive substrates, e.g. insulated metal substrate
• CPC Class Codes: H05K 1/056 the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/0909 Preformed cutting or breaking line
• CPC Class Codes: H05K 2201/09154 Bevelled, chamferred or tapered edge
• CPC Class Codes: H05K 2201/09745 Recess in conductor, e.g. in pad or in metallic substrate
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/44 : Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits H05K3/0058, H05K3/4608, and H05K3/4641 take precedence
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.

Claims

1. A circuit substrate comprising:

a metal substrate comprising a top surface, a bottom surface, a first side surface and a second side surface;

an insulating layer covering the top surface of the metal substrate; and

a conductive pattern formed on the insulating layer,

wherein the first side surface comprises a first inclining side surface inclining from the top surface and a second inclining side surface inclining from the bottom surface, and the first inclining side surface is shorter in a corresponding inclining direction thereof than the second inclining side surface in a corresponding inclining direction thereof.

2. The circuit substrate of claim 1, wherein the second side surface comprises a third inclining side surface inclining from the top surface and a fourth inclining side surface inclining from the bottom surface, and the third inclining side surface is longer in a corresponding inclining direction thereof than the fourth inclining side surface in a corresponding inclining direction thereof.

3. The circuit substrate of claim 1, further comprising a pad electrode formed on the insulating layer adjacent the first inclining side surface so that no other part of the conductive pattern is disposed between the pad electrode and the first inclining side surface.

4. The circuit substrate of claim 1, further comprising a circuit element disposed on the insulating layer and connected to the conductive pattern.

5. The circuit substrate of claim 3, further comprising a lead attached to the pad electrode.

6. The circuit substrate of claim 4, further comprising a sealing resin covering the circuit element and the insulating layer.

7. A circuit substrate comprising:

a metal substrate comprising a top surface, a bottom surface, a first side surface and a second side surface;

an insulating layer covering the top surface of the metal substrate; and

a conductive pattern formed on the insulating layer,

wherein the first side surface comprises a first inclining side surface inclining from the top surface, the second side surface comprises a second inclining side surface inclining from the top surface, and the first inclining side surface is shorter in a corresponding inclining direction thereof than the second inclining side surface in a corresponding inclining direction thereof.

8. The circuit substrate of claim 7, wherein the first side surface comprises a third inclining side surface inclining from the bottom surface, the second side surface comprises a fourth inclining side surface inclining from the bottom surface, and the third inclining side surface is longer in a corresponding inclining direction thereof than the fourth inclining side surface in a corresponding inclining direction thereof.

9. The circuit substrate of claim 7, further comprising a circuit element disposed on the insulating layer and connected to the conductive pattern.

10. The circuit substrate of claim 9, wherein the circuit element comprises a light emitting element.

11. The circuit substrate of claim 10, further comprising a sealing resin covering the light emitting element and the insulating layer.

12. A circuit substrate comprising:

a metal substrate comprising a top surface, a bottom surface, a first side surface, a second side surface opposite from the first side surface, a third side surface and a fourth side surface opposite from the third side surface;

an insulating layer covering the top surface of the metal substrate; and

a conductive pattern formed on the insulating layer,

wherein the first side surface comprises a first inclining side surface inclining from the top surface, the second side surface comprises a second inclining side surface inclining from the top surface, the third side surface comprises a third inclining side surface inclining from the top surface, the fourth side surface comprises a fourth inclining side surface inclining from the top surface, and the first and second inclining side surfaces are shorter in corresponding inclining directions thereof than the third and fourth inclining side surfaces in corresponding inclining directions thereof.

13. The circuit substrate of claim 12, wherein the first side surface comprises a fifth inclining side surface inclining from the bottom surface, the second side surface comprises a sixth inclining side surface inclining from the bottom surface, the third side surface comprises a seventh inclining side surface inclining from the bottom surface, the fourth side surface comprises a eight inclining side surface inclining from the bottom surface, and the fifth and sixth inclining side surfaces are longer in corresponding inclining directions thereof than the seventh and eighth inclining side surfaces in corresponding inclining directions thereof.

14. A method of manufacturing a circuit substrate, comprising:

providing a conductive pattern corresponding to a plurality of circuit units on a top surface of a substrate;

forming, in the top surface of the substrate, first grooves and second grooves that cross the first grooves and are shallower than the first groves so that the first and second grooves define regions of the circuit units;

forming, in a bottom surface of the substrate, third grooves and fourth grooves that cross the third grooves and are deeper than the third groves so that the third grooves correspond to the first grooves and the fourth grooves correspond to the second grooves; and

separating the circuit units from each other at the grooves.

15. The method of claim 14, wherein the forming of the conductive pattern comprises forming a pad electrode in each of the circuit unit at a peripheral portion thereof, and the second grooves are formed in a longitudinal direction of the circuit units.

16. The method of claim 14, wherein a depth of the first grooves and a depth of the fourth grooves are smaller than or equal to half a thickness of the substrate.

17. The method of claim 14, wherein an element is mounted on the substrate before the circuit units are separated.

18. A semiconductor device comprising:

a metal substrate comprising a top surface, a bottom surface and four side surfaces, the top surface being insulated;

a conductive pattern insulated from the metal substrate; and

a semiconductor element mounted on and electrically connected to the conductive pattern, wherein each of the side surfaces of the metal substrate comprises a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate; and

the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.

19. The semiconductor device of claim 18, wherein the metal substrate and the semiconductor element are covered with a sealing resin, and an input-output pad that is part of the conductive pattern is provided at least on one of the two opposing side surfaces of the pair.

20. The semiconductor device of claim 19, wherein the pad is provided in plurality on at least one of the two opposing side surfaces of the particular pair

wherein the metal substrate and the semiconductor element are covered with a sealing resin, and a plurality of input-output pads that are part of the conductive pattern are provided at least on one of the two opposing side surfaces of the pair.

21. The semiconductor device of claim 18, wherein the semiconductor element comprises a switching element that is used for an inverter circuit or a LED.