PROGRAMMABLE LATCH BASED MULTIPLIER

• US 20090167348A1
• Filed: 01/16/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Nij Dorairaj
• Inventors: DORAIRAJ, Nij
• Granted Patent: US 7,795,913 B2
• Time in Patent Office: Days
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.

Claims

1. A programmable logic circuit to implement a multiplier, comprising:

a latch comprising;

a latch input to receive a first data input;

a latch control input to receive a second data input;

a latch output generating an AND function of the latch input and the control input;

configuration memory elements coupled to the latch output; and

a logic block comprising;

an input coupled to the latch output;

one or more data inputs; and

a logic output to generate a partial logic term of a multiply operation.

2. The circuit of claim 1, wherein the control input is one of clock input, set input, and reset input.

3. The circuit of claim 1, wherein the first data input is a bit in a first data stream and the second data input is a bit in a second data stream and wherein the circuit implements the multiplication of the two data streams.

4. The circuit of claim 1, wherein the partial logic term is one of AND and XOR logic functions of latch output and one or more logic block data inputs.

5. The circuit of claim 1, wherein the logic block comprises a plurality of programmable inputs.

6. The circuit of claim 1, wherein the latch data input and latch control input are programmable.

7. The circuit of claim 1, wherein the logic block comprises one or more of:

programmable look-up-table (LUT) circuit, programmable multiplexer (MUX) circuit, programmable arithmetic logic circuit and programmable AND circuit and programmable NAND circuit.

8. The circuit of claim 1, wherein one or more of the inputs couple to a programmable interconnect matrix through one or more configurable multiplexer circuits.

9. The circuit of claim 1, comprising configuration memory elements coupled to the latch output.

10. The circuit of claim 1, wherein the configuration memory elements comprising one or more of SRAM, DRAM, EPROM, EEPROM, ROM, fuse-link, anti-fuse capacitor, magnetic, optical, ferro-electric, resistive, and mechanical memory elements.

11. A method of implementing a multiply logic function in a programmable logic block, the method comprising:

providing a first input to a programmable data input of a latch and a second input to a programmable control input of a latch;

generating an AND term of the first and second inputs at a latch output;

coupling the latch output and one or more data inputs to programmable inputs of a programmable logic block to generate a partial logic term of the inputs; and

providing configuration memory elements coupled to the latch output.

12. The method of claim 11, wherein the partial logic term computes one of:

AND function, OR function, NAND function, NOR function, NOT function of said logic block inputs.

13. The method of claim 11, comprising configuring a configurable multiplexer to couple the second input to the control input of the latch.

14. The method of claim 11, comprising configuring a configurable multiplexer to couple the latch output to a programmable logic block input.

15. The method of claim 11, comprising providing one or more of:

look-up-table (LUT), multiplexer circuit, NAND gate, NOR gate, AND gate, OR gate, XOR gate, product-term, register, processor, and Arithmetic-Logic-Unit circuit in the logic block.

16. The method of claim 11, comprising configuring one or more configuration memory elements.

17. The method of claim 15, wherein the configuration memory elements comprising one or more of SRAM, DRAM, EPROM, EEPROM, ROM, fuse-link, anti-fuse capacitor, magnetic, optical, ferro-electric, resistive, and mechanical memory elements.

18. A configurable circuit to implement a multiply logic function, the circuit comprising:

a logic block; and

a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input; and

configuration memory elements coupled to the latch output.

19. The circuit of claim 18 comprising a configuration circuit to configure the latch and the logic block.

20. The circuit of claim 18, comprising a configurable multiplexer coupled to the latch.