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PROGRAMMABLE LATCH BASED MULTIPLIER

  • US 20090167348A1
  • Filed: 01/16/2008
  • Published: 07/02/2009
  • Est. Priority Date: 12/26/2007
  • Status: Active Grant
First Claim
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1. A programmable logic circuit to implement a multiplier, comprising:

  • a latch comprising;

    a latch input to receive a first data input;

    a latch control input to receive a second data input;

    a latch output generating an AND function of the latch input and the control input;

    configuration memory elements coupled to the latch output; and

    a logic block comprising;

    an input coupled to the latch output;

    one or more data inputs; and

    a logic output to generate a partial logic term of a multiply operation.

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