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SIGNAL DELAY CIRCUIT

  • US 20090167399A1
  • Filed: 05/20/2008
  • Published: 07/02/2009
  • Est. Priority Date: 12/31/2007
  • Status: Active Grant
First Claim
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1. A signal delay circuit, comprising:

  • a capacitive load element, having a first input end receiving a first signal, a second input end receiving a second signal inverted to the first signal, and a third input end receiving a control signal, wherein the capacitance of the capacitive load element changes with the control signal.

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