SIGNAL DELAY CIRCUIT

• US 20090167399A1
• Filed: 05/20/2008
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: LU, Hung-Wen, SU, Chau-Chin
• Granted Patent: US 7,977,993 B2
• Time in Patent Office: Days
• US Class Current: 327/281
• CPC Class Codes: H03H 11/26 Time-delay networks analogue shift registers G11C27/04
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00228 having complementary input and output signals
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

Claims

1. A signal delay circuit, comprising:

a capacitive load element, having a first input end receiving a first signal, a second input end receiving a second signal inverted to the first signal, and a third input end receiving a control signal, wherein the capacitance of the capacitive load element changes with the control signal.

2. The signal delay circuit as claimed in claim 1, wherein the capacitive load element at least comprises three switches.

3. The signal delay circuit as claimed in claim 1, wherein the capacitive load element is an NAND gate.

4. The signal delay circuit as claimed in claim 3, wherein in a steady state, an N-type transistor in the NAND gate is turned off.

5. The signal delay circuit as claimed in claim 3, wherein when the first signal is approximately equal to the second signal, the N-type transistor in the NAND gate is slightly turned on.

6. The signal delay circuit as claimed in claim 3, further comprising an inverter for receiving and inverting the first signal, so as to output an inverted signal as the second signal.

7. The signal delay circuit as claimed in claim 3, further comprising:

a first inverter, for receiving a first input signal to output the first signal after inverting the first signal; and

a second inverter, for receiving a second input signal to output the second signal after inverting the second signal.

8. The signal delay circuit as claimed in claim 7, wherein the first input signal and the second input signal are differential input signals.

9. The signal delay circuit as claimed in claim 1, wherein the capacitive load element is an NOR gate.

10. The signal delay circuit as claimed in claim 9, further comprising an inverter for receiving and inverting the first signal, so as to output an inverted signal as the second signal.

11. The signal delay circuit as claimed in claim 9, further comprising:

a first inverter, for receiving a first input signal to output the first signal after inverting the first signal; and

a second inverter, for receiving a second input signal to output the second signal after inverting the second signal.

12. The signal delay circuit as claimed in claim 11, wherein the first input signal and the second input signal are differential input signals.

13. A signal delay circuit, comprising:

a first inverter, for receiving a first input signal to output the first signal after inverting the first signal; and

a second inverter, for receiving a second input signal to output the second signal after inverting the second signal, wherein the second signal is an inverted signal of the first signal, and the first input signal and the second input signal are differential input signals; and

more than one capacitive load element, each having a first input end receiving the first signal, a second input end receiving the second signal, and a third input end receiving a control signal, wherein the capacitance of the capacitive load element changes with the control signal.

14. The signal delay circuit as claimed in claim 13, wherein the capacitive load element at least comprises three switches.

15. The signal delay circuit as claimed in claim 13, wherein the capacitive load element is an NAND gate.

16. The signal delay circuit as claimed in claim 15, wherein in a steady state, an N-type transistor in the NAND gate is turned off.

17. The signal delay circuit as claimed in claim 15, wherein when the first signal is approximately equal to the second signal, the N-type transistor in the NAND gate is slightly turned on.

18. The signal delay circuit as claimed in claim 13, wherein the capacitive load element is an NOR gate.

19. The signal delay circuit as claimed in claim 13, wherein the first input signal and the second input signal are differential input signals.