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Digitally compensated highly stable holdover clock generation techniques using adaptive filtering

  • US 20090167443A1
  • Filed: 12/31/2007
  • Published: 07/02/2009
  • Est. Priority Date: 12/31/2007
  • Status: Active Grant
First Claim
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1. A system for generating a highly stable output clock signal, the system comprising:

  • an oven controlled crystal oscillator that generates a clock signal,a receiver that generates an input reference clock signal,a phase and frequency detector that generates an error signal based on the phase difference between the input reference clock signal and a feedback clock signal;

    a data storage block that stores model parameters to predict frequency variations of the clock signal generated by the oven controlled crystal oscillator,an adaptive filtering module containing a digital loop filter, a first defined algorithm for updating the model parameters stored in the data storage block, a second defined algorithm for predicting frequency variations of the clock signal generated by the oven controlled crystal oscillator based on value of the model parameters stored in the data storage block, and an output selector to generate a data signal,a switch that enables the system to operate either in normal mode by connecting the error signal to the adaptive filtering module when the input reference clock signal is available, or in holdover mode by breaking the connection of the error signal to the adaptive filtering module when the input reference clock signal is unavailable,a digitally controlled oscillator that operates with the oven controlled crystal oscillator as a reference clock, generates an output clock signal, and adjusts frequency of the output clock signal by adjusting its phase according to the data signal from the adaptive filtering module, anda feedback divider that divides the frequency of the output clock signal from the digitally controlled oscillator to generate the feedback clock signal when the system operates in the normal mode.

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