Digitally compensated highly stable holdover clock generation techniques using adaptive filtering

• US 20090167443A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Yong, Zhang, Liang, Liu, Xin
• Granted Patent: US 7,692,499 B2
• Time in Patent Office: Days
• US Class Current: 331/10
• CPC Class Codes: H03L 1/02 against variations of temperature only
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Claims

1. A system for generating a highly stable output clock signal, the system comprising:

an oven controlled crystal oscillator that generates a clock signal,

a receiver that generates an input reference clock signal,

a phase and frequency detector that generates an error signal based on the phase difference between the input reference clock signal and a feedback clock signal;

a data storage block that stores model parameters to predict frequency variations of the clock signal generated by the oven controlled crystal oscillator,

an adaptive filtering module containing a digital loop filter, a first defined algorithm for updating the model parameters stored in the data storage block, a second defined algorithm for predicting frequency variations of the clock signal generated by the oven controlled crystal oscillator based on value of the model parameters stored in the data storage block, and an output selector to generate a data signal,

a switch that enables the system to operate either in normal mode by connecting the error signal to the adaptive filtering module when the input reference clock signal is available, or in holdover mode by breaking the connection of the error signal to the adaptive filtering module when the input reference clock signal is unavailable,

a digitally controlled oscillator that operates with the oven controlled crystal oscillator as a reference clock, generates an output clock signal, and adjusts frequency of the output clock signal by adjusting its phase according to the data signal from the adaptive filtering module, and

a feedback divider that divides the frequency of the output clock signal from the digitally controlled oscillator to generate the feedback clock signal when the system operates in the normal mode.

2. The system of claim 1, wherein the output selector in the adaptive filtering module comprises a multiplexer.

3. The system of claim 1, wherein the model parameters stored in the data storage block indicating the frequency variations include two sets, one due to temperature perturbation and the other due to aging effects of the oven controlled crystal oscillator.

4. The system of claim 1, when the system operates in normal mode, the adaptive filtering module receives the error signal from the phase and frequency detector, wherein the digital loop filter is used to filter the error signal and the first defined algorithm is utilized to update the two sets of model parameters, and the adaptive filtering module outputs a data signal representing the filtered error signal.

5. The system of claim 1, when the system operates in holdover mode, the adaptive filtering module utilizes the second defined algorithm for predicting frequency variations of the clock signal generated by the oven controlled crystal oscillator based on value of the model parameters stored in the data storage block, and outputs a data signal representing predicted frequency variations.

6. The system of claim 1, wherein the receiver is a Global Positioning System receiver which generates a GPS based frequency signal.

7. The system of claim 1, wherein the data storage block comprises an Electrically Erasable Programmable Read-Only Memory.

8. The system of claim 1, wherein the first and second defined algorithms are realized by software running on an embedded microprocessor.

9. The system of claim 1, wherein the first and second defined algorithms are realized by Hardware Description Language and synthesized into a gate level netlist.

10. A method for generating an output clock signal, the method comprising:

generating an input reference clock signal;

when the input reference clock signal is available,

generating a feedback clock signal,

generating an error signal representing phase difference between the input reference clock-signal and the feedback clock signal,

generating and locking the frequency of the output clock signal to the frequency of the input reference clock signal based on the error signal,

storing two sets of model parameters indicating frequency variations due to aging effects and temperature perturbation of an oven controlled crystal oscillator in a data storage block,

updating the two sets of model parameters based on a defined algorithm, when the input reference clock signal is unavailable,

generating the output clock signal based on clock signal of the oven controlled crystal oscillator and values of the two sets of model parameters stored in the data storage block.