ANALOG-TO-DIGITAL CONVERTER

• US 20090167587A1
• Filed: 02/02/2007
• Published: 07/02/2009
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Wu, Honglei, Xu, Yong Ping
• Granted Patent: US 7,834,796 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: H03M 1/466 using switched capacitors

Abstract

An analog-to-digital converter (ADC) and a battery operated electronic device comprising the ADC. The ADC comprising an input switch; an array of binary-weighted capacitors, the array of capacitors receiving the input voltage signal via the input switch in an on state of the input switch; a plurality of switches, each switch connected in series with a respective one of the capacitors at an opposite side compared to the input switch, wherein a VDD signal is applied to each switch in one switching state and ground in another switching state; a comparator having as one input a voltage from the input switch side of the array of capacitors and as another input a voltage of VDD/2; and a switch control unit coupled to an output of the comparator for controlling the switches based on the output from the comparator.

Claims

1. An analog-to-digital converter (ADC) comprising:

an input switch;

an array of binary-weighted capacitors, the array of capacitors receiving the input voltage signal via the input switch in an on state of the input switch;

a plurality of switches, each switch connected in series with a respective one of the capacitors at an opposite side compared to the input switch, wherein a V_DD signal is applied to each switch in one switching state and ground in another switching state;

a comparator having as one input a voltage from the input switch side of the array of capacitors and as another input a voltage of V_DD/2; and

a successive approximation register (SAR) coupled to an output of the comparator for controlling the switches based on the output from the comparator.

2. The ADC as claimed in claim 1, wherein the input switch is in an on state prior to analog-to-digital conversion to provide the input voltage to the array of binary-weighted capacitors and is in an off state during the analog-to-digital conversion.

3. The ADC as claimed in claim 2, wherein, at the beginning of the analog-to-digital conversion, the switch connected to a Most Significant Bit (MSB) one of the capacitors is switched to the V_DD signal and all other switches are switched to ground.

4. The ADC as claimed in claim 3, wherein the switch connected to the MSB capacitor is switched to ground for subtracting about V_DD/2 from the input voltage if the comparator determines that the voltage from the input switch side of the array of capacitors is greater than V_DD/2 or to V_DD if the voltage from the input switch side of the array of capacitors is lower than or equal to V_DD/2.

5. The ADC as claimed in claim 4, wherein, when the MSB capacitor is switched to ground for subtracting about V_DD/2 from the input voltage, the voltage at the input switch side of the array of capacitors is reduced to within a range of about 0 to about V_DD/2.

6. The ADC as claimed in claim 4, wherein, in a register sequence, the switch connected to a next lower bit capacitor is then switched to the V_DD signal and said next switch is switched to ground if the comparator determines that the voltage from the input switch side of the array of capacitors is greater than V_DD/2 or to V_DD if the voltage from the input switch side of the array of capacitors is lower than or equal to V_DD/2.

7. The ADC as claimed in claim 6, wherein said register sequence is sequentially applied to all switches.

8. The ADC as claimed in claim 7, wherein, after the switch connected to a Least Significant Bit (LSB) capacitor has been subjected to the register sequence, the input switch is closed to provide a new input signal to the array of capacitors.

9. The ADC as claimed in claim 1, wherein the input switch is implemented as a sampling switch.

10. The ADC as claimed in claim 9, wherein the sampling switch comprises an n- and p-transistor pair.

11. The ADC as claimed in claim 1, wherein the input switch is implemented in an output stage of a Low Noise Operational Transconductance Amplifier (LN-OTA) coupled to the ADC.

12. The ADC as claimed in claim 11, wherein the input switch is implemented by a pair of switch elements in the output stage of the LN-OTA coupled to the ADC.

13. A battery operated electronic device comprising an ADC as claimed in claim 1.

14. The battery operated electronic device as claimed in claim 13, wherein the device is a medical device for electroencephalograms (EEG) and electrocardiograms (ECG).