LCD DRIVER IC AND METHOD FOR OPERATING THE SAME

• US 20090167746A1
• Filed: 12/17/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Yoon, Jang Hyun
• Granted Patent: US 8,451,261 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

Disclosed is an LCD driver IC including: a POR (Power On Reset) circuit; and a counter, which receives a signal from the POR circuit to delay time and releases a RESETB of the POR circuit after power of a gate driver IC is stabilized.

Claims

1. An LCD driver IC, comprising:

a POR (Power On Reset) circuit; and

a counter circuit, which receives a signal from the POR circuit to delay time and releases a RESETB output signal of the POR circuit after power of a gate driver IC is stabilized.

2. The LCD driver IC according to claim 1, wherein the counter circuit allows an output of the gate driver chip to maintain a VGL state during a 3-frame time.

3. The LCD driver IC according to claim 2, wherein the output of the gate driver IC maintains the VGL state while 2048 CPV clock signals (gate clock signal) are being counted by a counter of the counter circuit.

4. The LCD driver IC according to claim 1, the counter circuit outputs a RESETB for the gate driver IC after VGH and VGL are stabilized.

5. The LCD driver IC according to claim 1, wherein a static current of the POR circuit is zero.

6. The LCD driver IC according to claim 5, wherein the POR circuit comprises a four transistor modified schmitt trigger.

7. The LCD driver IC according to claim 1, wherein the counter circuit comprises:

a first counter receiving the signal from the POR circuit to delay a first time;

a first flip flop, wherein an output of the first counter is connected to a clock input of the first flip flop;

a first AND gate, wherein an output of the first flip flop is connected to a first input of the first AND gate and the signal from the POR circuit is connected to a second input of the first AND gate;

a second counter receiving an output from the first AND gate to delay a second time; and

a second flip flop, wherein an output of the second counter is connected to a clock input of the second flip flop,

wherein after the second delay, an output of the second flip flop releases the RESETB output signal.

8. The LCD driver IC according to claim 7, wherein the first counter is an 8 Counter and the second counter is a 2048 Counter.

9. The LCD driver IC according to claim 7, further comprising:

an inverter receiving the output of the second counter; and

a second AND gate, wherein a first input of the second AND gate receives a CLK signal and a second input of the second AND gate receives an output of the inverter, wherein an output of the second AND gate is connected to the first counter and the second counter to reset the first and second counters.

10. The LCD driver IC according to claim 1, wherein the POR circuit comprises:

a first PMOS transistor having a source connected to a VDD and a drain connected to an input of a first inverter;

a first NMOS transistor having a drain connected to the input of the first inverter;

a second NMOS transistor having a source connected to a ground, a drain connected to a source of the first NMOS transistor, and a gate connected to a gate of the first NMOS transistor and a gate of the first PMOS transistor; and

a third NMOS transistor having a gate connected to an output of the first inverter, a source connected to the drain of the second NMOS transistor, and a drain connected to the VDD.

11. A method for operating an LCD driver IC, the method comprising:

operating a POR circuit;

counting signals using a counter until all powers of a gate driver IC are stabilized after the operation of the POR circuit; and

releasing a RESETB of the gate driver IC after all the powers are stabilized.

12. The method according to claim 11, in the step of counting the signals until all of the powers are stabilized, an output of the gate driver IC is set to a VGL state while the signals are being counted during a 3-frame time.

13. The method according to claim 12, in the step of releasing the RESETB of the gate driver IC, a flip flop of the gate driver IC is released after 2048 CPV clock signals are counted.