Three dimensional hexagonal matrix memory array

• US 20090168480A1
• Filed: 12/27/2007
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Petti, Christopher J.
• Granted Patent: US 7,746,680 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G03F 7/2022 Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells

Abstract

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Claims

1. A nonvolatile memory device, comprising a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern.

2. The nonvolatile memory device of claim 1, wherein:

the plurality of nonvolatile memory cells comprises a plurality of pillar shaped current steering elements; and

the substantially hexagonal pattern comprises a repeating pattern of seven nonvolatile memory cells having a central nonvolatile memory cell surrounded by six other nonvolatile memory cells arranged in a hexagonal layout around the central nonvolatile memory cell.

3. The nonvolatile memory device of claim 1, wherein the device comprises:

a first nonvolatile memory cell,

a second nonvolatile memory cell, and

a third nonvolatile memory cell;

wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell are equidistant from each other and are located in a same plane.

4. The nonvolatile memory device of claim 3, wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell have a cell half pitch of less than about 32 nm.

5. The nonvolatile memory device of claim 1, wherein the device comprises a monolithic, three dimensional array of nonvolatile memory cells.

6. The nonvolatile memory device of claim 1, wherein each nonvolatile memory cell comprises a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

7. The nonvolatile memory device of claim 1, further comprising:

at least one bit line; and

at least one word line;

wherein the at least one bit line and the at least one word line are located in two different planes, and wherein the at least one word line crosses the at least one bit line at an angle of about 60 degrees.

8. The nonvolatile memory device of claim 1, wherein the nonvolatile memory cells are arranged in a plurality of subarrays which are substantially parallelogram shaped and have a non-square corner.

9. A nonvolatile memory device, comprising:

a plurality of word lines;

a plurality of bit lines; and

a nonvolatile memory cell array comprising a plurality of nonvolatile memory cells;

wherein;

the plurality of word lines cross the plurality of bit lines at an angle of about 60 degrees in the memory cell array; and

the plurality of nonvolatile memory cells in the nonvolatile memory cell array are arranged in a plurality of subarrays which are substantially parallelogram shaped.

10. The nonvolatile memory device of claim 9, wherein in each subarray of the plurality of subarrays, the plurality of word lines extend substantially parallel to first and second sides of the subarray and the plurality of bit lines extend substantially parallel to third and fourth sides of the subarray.

11. The nonvolatile memory device of claim 10, wherein respective third sides of adjacent subarrays extend at an angle of about 120 degrees with respect to each other such that adjacent subarrays form a substantial mirror image of each other about a mirror plane extending parallel to the first and second sides of the adjacent subarrays.

12. The nonvolatile memory device of claim 10, wherein the nonvolatile memory cell array comprises a monolithic, three dimensional array of nonvolatile memory cells.

13. The nonvolatile memory device of claim 12, further comprising:

a plurality of bit line driver circuits, wherein the plurality of bit line driver circuits are located on a different level from the plurality of nonvolatile memory cells, and wherein each the bit line driver circuit occupies a staggered area that straddles a projection of the third or the fourth side of a respective subarray;

a plurality of word line driver circuits, wherein the plurality of word line driver circuits are located on a different level from the plurality of nonvolatile memory cells, and wherein each the word line driver circuit occupies an area that straddles a projection of the first or the second side of a respective subarray;

a plurality of vertical bit line connections that connect the plurality of bit line driver circuits to the plurality of bit lines; and

a plurality of vertical word line connections that connect the plurality of word line driver circuits to the plurality of word lines.

14. The nonvolatile memory device of claim 13, wherein at least one of the plurality of vertical bit line connections extends vertically between the first side of a first subarray and the second side of an adjacent second subarray, and the at least one of the plurality of the vertical word line connections extends vertically between the third side of the first subarray and the fourth side of an adjacent third subarray.

15. The nonvolatile memory device of claim 9, wherein the plurality of subarrays are arranged in a substantially rectangular shape on a die.

16. The nonvolatile memory device of claim 9, wherein the plurality of nonvolatile memory cells are arranged in a substantially hexagonal pattern in each subarray of the plurality of subarrays.

17. A method of making a device, comprising:

forming a self-assembling material layer over at least one device layer, wherein the self-assembling material forms a plurality of openings that expose a first surface of the at least one device layer;

forming a hard mask material layer over the self-assembling material layer such that the hard mask material fills the plurality of openings;

removing the hard mask material such that the hard mask material patterns remain in the plurality of openings and an upper surface of the self-assembling material layer is exposed;

removing the self-assembling material layer; and

etching the at least one device layer using the hard mask material patterns as a mask to form a plurality of pillar shaped devices.

18. The method of claim 17, wherein the at least one device layer comprises at least one layer of a memory cell material and the plurality of pillar shaped devices comprise a plurality of pillar shaped nonvolatile memory devices.

19. The method of claim 17, wherein:

the step of removing the hard mask material comprises isotropically etching the hard mask material; and

the self-assembling material comprises a polystyrene and polymethylmethacrylate diblock copolymer.

20. The method of claim 17, wherein the self-assembling material forms a plurality of openings in a substantially hexagonal pattern by self-assembly and the plurality of pillar shaped devices are arranged in a substantially hexagonal pattern.