THREE-DIMENSIONAL MEMORY DEVICE

• US 20090168482A1
• Filed: 12/24/2008
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Yeong-Taek, PARK, Ki-Tae, KIM, Doo-Gon
• Application Number:
  US12/343,630
• Publication Number:
  US 20090168482A1
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally includes passive elements

Claims

1. A three-dimensional memory device comprising:

a base layer comprising a memory array and peripheral circuits formed on a bulk silicon substrate; and

N circuit layers, where N is a positive integer, each comprising a memory array formed on a silicon-on-insulator (SOI) substrate,

wherein the N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally comprises passive elements.

2. The three-dimensional memory device of claim 1, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are driven by the peripheral circuits.

3. The three-dimensional memory device of claim 1, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are respectively configured to share at least one bit line.

4. The three-dimensional memory device of claim 1, wherein the passive elements comprise decoupling capacitors and resistors associated with signal lines extending from the peripheral circuits.

5. The three-dimensional memory device of claim 1, wherein the Nth layer further comprises input/output pads.

6. The three-dimensional memory device of claim 1, wherein each one of the N circuit layers comprises input/output pads.

7. A three-dimensional memory device comprising:

a base layer comprising a memory array and passive circuits formed on a bulk silicon substrate; and

N circuit layers, where N is a positive integer, each comprising a memory array formed on a silicon-on-insulator (SOI) substrate,

wherein the N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally comprises peripheral circuits.

8. The three-dimensional memory device of claim 7, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are driven by the peripheral circuits.

9. The three-dimensional memory device of claim 7, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are respectively configured to share at least one bit line.

10. The three-dimensional memory device of claim 7, wherein the passive elements comprise decoupling capacitors and resistors associated with signal lines extending from the peripheral circuits.

11. The three-dimensional memory device of claim 7, wherein the base layer further comprises input/output pads.

12. The three-dimensional memory device of claim 7, wherein each one of the N circuit layers comprises input/output pads.

18. The three-dimensional memory device of claim 12, wherein the first and second peripheral circuits are disposed overlapping one another.

19. The three-dimensional memory device of claim 18, wherein the first and second passive elements are disposed overlapping one another.

13. A three-dimensional memory device comprising:

a base layer comprising a memory array, first peripheral circuits, and first passive elements formed on a bulk silicon substrate; and

N circuit layers, where N is a positive integer, each comprising a memory array formed on a silicon-on-insulator (SOI) substrate,

wherein the N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally comprises second peripheral circuits and second passive elements.

14. The three-dimensional memory device of claim 13, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are driven by at least one of the first and second peripheral circuits.

15. The three-dimensional memory device of claim 13, wherein the memory array of the base layer and the respective memory arrays of the N circuit layers are respectively configured to share at least one bit line.

16. The three-dimensional memory device of claim 13, wherein the memory array of the base layer is associated with a first set of bit lines and at least one of the respective memory arrays of the N circuit layers is associated with a second set of bit lines different from the first set of bit lines.

17. The three-dimensional memory device of claim 13, wherein the first and second passive elements comprise decoupling capacitors and resistors associated with signal lines extending from at least one of the first and second peripheral circuits.