SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE

• US 20090168495A1
• Filed: 03/05/2009
• Published: 07/02/2009
• Est. Priority Date: 09/05/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: AOKI, Masaki
• Granted Patent: US 7,898,839 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage.

Claims

1. A method of writing into a semiconductor memory device comprising:

writing a low resistance state at once in resistance memory elements of memory cells to be written connected to one of a plurality of word lines; and

writing a high resistance state selectively in the resistance memory element of the memory cell connected to the one of the plurality of word lines which the low resistance state has been written in and the high resistance state is to be written in,

wherein the semiconductor memory device includes;

a plurality of memory cells laid out in a matrix each including the resistance memory element which memorizes the high resistance state and the low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, and a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage;

a plurality of bit lines which are a plurality of signal lines extended in a first direction and in parallel with each other, the respective signal lines being connected to the other ends of the resistance memory elements of the memory cells laid out in the first direction;

the plurality of word lines which are a plurality of signal lines extended in a second direction intersecting the first direction and in parallel with each other, the respective signal lines being connected to gate terminals of the first transistors of the memory cells laid out in the second direction; and

a plurality of second transistors which are a plurality of transistors respectively connected to the plurality of bit lines, the respective transistors having a source terminal connected via the bit line to the other ends of the resistance memory elements of the memory cells laid out in the first direction and a drain terminal a write voltage is applied to.

2. The method of writing into the semiconductor memory device according to claim 1, wherein

in writing the high resistance state, the high resistance state is written at once in the resistance memory elements of the memory cells for the high resistance state to be written in.

3. The method of writing into the semiconductor memory device according to claim 1, further comprising:

verifying whether or not the high resistance state has been written in the resistance memory element of the memory cell for the high resistance state to be written in; and

rewriting the high resistance state in the resistance memory element of the memory cell for the high resistance state to be written in, when the high resistance state has not been written in the resistance memory element of the memory cell for the high resistance state to be written in.

4. The method of writing into the semiconductor memory device according to claim 3, wherein

in rewriting the high resistance state, the drive voltage to be applied to a gate terminal of the second transistor is increased than in writing the high resistance state.

5. The method of writing into the semiconductor memory device according to claim 1, wherein

in writing the low resistance state, a voltage to be applied to the one word line is so controlled that a channel resistance of the first transistor of the respective memory cells to be written is sufficiently smaller than a resistance value of the resistance memory element in the high resistance state and sufficiently larger than a resistance value of the resistance memory element in the low resistance state.

6. The method of writing into the semiconductor memory device according to claim 5, wherein

in writing the low resistance state, a current to flow when the resistance memory elements have been switched to the low resistance state is limited by the first transistors.

7. The method of writing into the semiconductor memory device according to claim 5, wherein

in writing the low resistance state, a drive voltage, which is higher by a threshold voltage of the second transistor than the write voltage, is applied to a gate terminal of the respective second transistors.

8. The method of writing into the semiconductor memory device according to claim 5, wherein

in writing the low resistance state, the write voltage is set at a power source voltage, a voltage to be applied to a gate terminal of the respective second transistors is set at a value which is the total of the power source voltage and a threshold voltage of the second transistor, and a voltage to be applied to the one word line is set at a value which is lower than the power source voltage.

9. The method of writing into the semiconductor memory device according to claim 1, wherein

in writing the high resistance state, a voltage to be applied to the resistance memory element is controlled to be a value which is not less than the reset voltage and less than the set voltage by applying to a gate terminal of the second transistors connected to the bit line associated with the memory cell for the high resistance state to be written in a voltage which is not less than a total of a reset voltage of the resistance memory element and a threshold voltage of the second transistor and is less than a total of a set voltage of the resistance memory element and the threshold voltage.

10. The method of writing into the semiconductor memory device according to claim 9, wherein

in writing the high resistance state, the write voltage is set at a value which is not less than a total of the reset voltage of the resistance memory element and the threshold voltage.

11. The method of writing into the semiconductor memory device according to claim 9, wherein

in writing the high resistance state, the write voltage, the voltage to be applied to the gate terminal of the second transistor, and the voltage to be applied to the one word line are set at a power source voltage.

12. The method of writing into the semiconductor memory device according to claim 9, wherein

in writing the high resistance state, the voltage to be applied to the one word line is set so that a channel resistance of the respective first transistors has a value which is sufficiently small with respect to a resistance value of the resistance memory element in the low resistance state.

13. The method of writing into the semiconductor memory device according to claim 1, wherein

a constant voltage is applied to the one word line, and

the write voltage of a pulse voltage is applied to the drain terminal of the second transistor.

14. The method of writing into the semiconductor memory device according to claim 1, wherein

a pulse voltage is applied to the one word line, and

the write voltage of a constant voltage is applied to the drain terminal of the second transistor.

15. The method of writing into the semiconductor memory device according to claim 1, wherein

the semiconductor memory device is a memory for input/output data of multi-bit, and

an information corresponding to respective bits of the input/output data is written in the plurality of memory cells to be written.

16. A method of writing into a semiconductor memory device comprising:

writing a high resistance state at once in resistance memory elements of memory cells to be written connected to one of a plurality of word lines; and

writing a low resistance state selectively in the resistance memory element of the memory cell connected to the one of the plurality of word lines which the high resistance state has been written in and the low resistance state is to be written in,

wherein the semiconductor memory device includes;

a plurality of memory cells laid out in a matrix each including the resistance memory element which memorizes the high resistance state and the low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, and a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage;

a plurality of bit lines which are a plurality of signal lines extended in a first direction and in parallel with each other, the respective signal lines being connected to the other ends of the resistance memory elements of the memory cells laid out in the first direction;

the plurality of word lines which are a plurality of signal lines extended in a second direction intersecting the first direction and in parallel with each other, the respective signal lines being connected to gate terminals of the first transistors of the memory cells laid out in the second direction; and

a plurality of second transistors which are a plurality of transistors respectively connected to the plurality of bit lines, the respective transistors having a source terminal connected via the bit line to the other ends of the resistance memory elements of the memory cells laid out in the first direction and a drain terminal a write voltage is applied to.

17. The method of writing into the semiconductor memory device according to claim 16, further comprising:

verifying whether or not the low resistance state has been written in the resistance memory element of the memory cell for the low resistance state to be written in; and

rewriting the low resistance state in the resistance memory element of the memory cell for the low resistance state to be written in, when the low resistance state has not been written in the resistance memory element of the memory cell for the low resistance state to be written in.

18. The method of writing into the semiconductor memory device according to claim 17, wherein

in rewriting the low resistance state, the drive voltage to be applied to a gate terminal of the second transistor is increased than in writing the low resistance state.