Flash memory device and reading method thereof

• US 20090168511A1
• Filed: 12/15/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Yong-Hoon
• Granted Patent: US 8,018,777 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells.

Claims

1. A flash memory comprising:

a memory cell array having memory cells arranged at intersections of word lines and bit lines such that at least one bit line is associated with a plurality of memory cells connected in series;

a voltage generator configured to generate a selection voltage and at least a first non-selection voltage;

a row selection circuit configured to drive the word lines based on at least the selection voltage and the first non-selection voltage; and

a control logic circuit configured to control operation of the voltage generator and the row selection circuit such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells, the selected memory cell being a memory cell in the plurality of memory cells connected to the word line receiving the selection voltage.

2. The flash memory as set forth in claim 1, wherein the control circuit is configured to control the row selection circuit to apply the first non-selection voltage to the word lines associated with memory cells subsequent to the selected memory cell in the plurality of memory cells.

3. The flash memory as set forth in claim 2, wherein the plurality of memory cells connected in series are between a series selection transistor and a ground selection transistor.

4. The flash memory as set forth in claim 3, wherein the control circuit is configured to control the voltage generator to increase the first non-selection voltage as the selected memory cell is located closer to the series selection transistor.

5. The flash memory as set forth in claim 3, wherein the control circuit is configured to control the voltage generator to decrease the first non-selection voltage as the selected memory cell is located closer to the ground selection transistor.

6. The flash memory as set forth in claim 2, wherein the control circuit is configured to control the row selection circuit to apply a standard non-selection voltage to the word lines associated with memory cells prior to the selected memory cell in the plurality of memory cells.

7. A flash memory device comprising:

a memory cell array having memory cells arranged at intersections of word lines and bit lines such that at least one bit line is associated with a plurality of memory cells connected in series;

a voltage generator configured to generate a selection voltage, a first non-selection voltage, and a second non-selection voltage;

a row selection circuit configured to drive the word lines based on the selection voltage, the first non-selection voltage, and the second non-selection voltage; and

a control logic circuit configured to control operation of the voltage generator and row selection circuit such that the voltage generator generates the first non-selection voltage and second non-selection voltage based on a location of a selected memory cell in the plurality of memory cells, the selected memory cell being a memory cell in the plurality of memory cells connected to the word line receiving the selection voltage.

8. The flash memory as set forth in claim 7, wherein the control circuit is configured to control the row selection circuit to (1) apply the first non-selection voltage to the word lines associated with memory cells subsequent to the selected memory cell in the plurality of memory cells, and (2) apply the second non-selection voltage to the word lines associated with memory cells prior to the selected memory cell in the plurality of memory cells.

9. The flash memory as set forth in claim 8, wherein the plurality of memory cells connected in series are between a series selection transistor and a ground selection transistor.

10. The flash memory as set forth in claim 9, wherein the control circuit is configured to control the voltage generator to increase the first non-selection voltage and decrease the second non-selection voltage as the selected memory cell is located closer to the series selection transistor.

11. The flash memory as set forth in claim 9, wherein the control circuit is configured to control the voltage generator to decrease the first non-selection voltage and increase the second non-selection voltage as the selected memory cell is located closer to the ground selection transistor.

12. A flash memory comprising:

a memory cell array having memory cells arranged at intersections of word lines and bit lines such that at least one bit line is associated with a plurality of memory cells connected in series;

a voltage generator configured to generate a selection voltage and at least a first non-selection voltage;

a row selection circuit configured to drive the word lines based on the selection voltage and the first non-selection voltage; and

a control logic circuit configured to control operation of the voltage generator and the row selection circuit such that the voltage generator generates the first non-selection voltage based on the number of memory cells subsequent to a selected memory cell, the selected memory cell being a memory cell in the plurality of memory cells connected to the word line receiving the selection voltage.

13. The flash memory as set forth in claim 12, wherein the control circuit is configured to control the row selection circuit to apply the first non-selection voltage to the word lines associated with memory cells subsequent to the selected memory cell in the plurality of memory cells.

14. The flash memory as set forth in claim 13, wherein the control circuit is configured to control the voltage generator to increase the first non-selection voltage as the number of memory cells subsequent to the selected memory cell in the plurality of memory cells increases.

15. The flash memory as set forth in claim 13, wherein the control circuit is configured to control the voltage generator to decrease the first non-selection voltage as a number of memory cells prior to the selected memory cell in the plurality of memory cells increases.

16. The flash memory as set forth in claim 12, wherein the control circuit is configured to control operation of the voltage generator and the row selection circuit such that the voltage generator generates a second non-selection voltage based on the number of memory cells prior to a selected memory cell.

17. The flash memory as set forth in claim 16, wherein the control circuit is configured to control the row selection circuit to (1) apply the first non-selection voltage to the word lines associated with memory cells subsequent to the selected memory cell in the plurality of memory cells, and (2) apply the second non-selection voltage to the word lines associated with memory cells prior to the selected memory cell in the plurality of memory cells.

18. The flash memory as set forth in claim 17, wherein the control circuit is configured to control the voltage generator to increase the first non-selection voltage and decrease the second non-selection voltage as the number of memory cells subsequent to the selected memory cell in the plurality of memory cells increases.

19. The flash memory as set forth in claim 17, wherein the control circuit is configured to control the voltage generator to decrease the first non-selection voltage and increase the second non-selection voltage as the number of memory cells prior to the selected memory cell in the plurality of memory cells increases.