MULTIPLE LEVEL CELL MEMORY DEVICE WITH IMPROVED RELIABILITY

• US 20090168513A1
• Filed: 03/31/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanaka, Tomoharu
• Application Number:
  US12/059,572
• Publication Number:
  US 20090168513A1
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

The reliability of multiple level cells in a memory device should be increased by programming the ends of the series strings of memory cells differently than the remaining quantity of memory cells of the series string. The end cells closest to select gate source and select gate drain transistors can be programmed as single level cells while the remaining cells of the string are programmed as multiple level cells. Another embodiment can program only one or more cells at the source end of the series string as single level cells. Still another embodiment can skip programming of the cells at either only the source end or both the source end and the drain end of the series string.

Claims

1. A series string of memory cells comprising:

a first end coupled to a transfer line;

a second end coupled to a source; and

a plurality of memory cells coupled between the first end and the second end wherein at least one memory cell closest to the second end is programmed to a different bit density than a majority of the plurality of memory cells.

2. The series string of memory cells of claim 1 wherein the at least one memory cell is programmed as a single level cell and the remainder of the plurality of memory cells are programmed as multiple level cells.

3. The series string of memory cells of claim 1 wherein a subset of the plurality of memory cells closest to the second end is programmed as single level cells and the remainder of the plurality of memory cells are programmed as multiple level cells.

4. The series string of memory cells of claim 1 wherein a first subset of the plurality of memory cells closest to the second end is programmed as single level cells, a second subset of the plurality of memory cells closest to the first end is programmed as single level cells, and the remainder of the plurality of memory cells are programmed as multiple level cells.

5. The series string of memory cells of claim 4 wherein the first and second subsets are each comprised of two memory cells.

6. The series string of memory cells of claim 4 wherein the first and second subsets are each comprised of one memory cell.

7. The series string of memory cells of claim 1 and further including:

a select gate drain transistor coupled between the first end and the bit line; and

a select gate source transistor coupled between the second end and the source line.

8. A series string of memory cells comprising:

a first end coupled through a select gate drain transistor to a bit line;

a second end coupled through a select gate source transistor to a source line; and

a plurality of memory cells coupled between the first end and the second end wherein a first memory cell closest to the select gate source transistor is not used and a remainder of the plurality of memory cells is programmed as multiple level cells.

9. The series string of memory cells of claim 8 wherein a second memory cell closest to the select gate drain transistor is not used.

10. The series string of memory cells of claim 8 wherein the at least one of the memory cells is programmed and/or read in accordance with a different number of potential states than the majority of the plurality of memory cells.

11. The series string of memory cells of claim 8 wherein a second memory cell, adjacent to the first memory cell is programmed at a lower bit density than the remainder of the plurality of memory cells and a third memory cell closest to the select gate drain transistor is programmed at the lower bit density.

12. The series string of memory cells of claim 11 wherein the lower bit density is single level cell.

13. A memory device comprising:

control circuitry for controlling operation of the memory device; and

a memory array, coupled to the control circuitry, comprising;

a plurality of series strings of memory cells, each series string comprising a first end and a second end and a plurality of memory cells between the first and second ends wherein a first subset of the plurality of memory cells is adjacent to the first end and a second subset of the plurality of memory cells is adjacent to the second end and a remaining quantity of memory cells between the first and second subsets are programmed to a higher bit density than the first and second subsets.

14. The memory device of claim 13 wherein the memory device is a NAND flash memory device.

15. The memory device of claim 13 wherein both the first and second subsets are each comprised of two memory cells and are programmed as single level cells and the remaining quantity of memory cells are programmed as multiple level cells.

16. The memory device of claim 13 and further including:

a select gate drain transistor coupling the first end to a bit line;

a select gate source transistor coupling the second end to a source line; and

a word line that couples rows of adjacent series strings of memory cells.

17. The memory device of claim 13 wherein the first and second subsets are each comprised of one memory cell and are not used.

18. The memory device of claim 13 wherein the first subset is comprised of one memory cell that is programmed as a single level cell and the second subset is comprised of two memory cells wherein a first cell that is adjacent to a select gate source transistor is not used, the second cell is programmed as a single level cell, and the remaining quantity of memory cells of the series string are programmed as multiple level cells.

19. A method for programming a memory device, the method comprising:

programming at a first bit density at least one memory cell, of a series string of memory cells, closest to a source line of the memory device; and

programming a remaining quantity of memory cells of the series string of memory cells at a second bit density that is higher than the first bit density.

20. The method of claim 19 wherein programming at the first bit density comprises:

programming, at the first bit density, two memory cells at a first end closest to the source line; and

programming, at the first bit density, two memory cells at a second end of the series string of memory cells that are closest to a bit line.

21. The method of claim 19 wherein programming at the first bit density comprises programming as a single level cell and programming at the second bit density comprises programming as a multiple level cell.

22. The method of claim 19 wherein programming at the first bit density comprises programming, at the first bit density, two memory cells at a first end closest to the source line.

23. The method of claim 19 wherein programming at the first bit density comprises:

programming, at the first bit density, one memory cell at a first end closest to the source line; and

programming, at the first bit density, one memory cell at a second end of the series string of memory cells closest to a bit line.

24. A memory device comprising;

control circuitry for controlling operation of the memory device; and

a memory array, coupled to the control circuitry, comprising;

a plurality of series strings of memory cells, each series string comprising a first end and a second end and a plurality of memory cells between the first and second ends wherein the number of the memory cells is more than 2^N and less than 2^M wherein (M=N+1), and the controller is configured to control the memory cells on a cell-by-cell basis.

25. The memory device of claim 24 wherein N is device specific, is determined at manufacture of the device and wherein N=5.