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Architecture of a nvDRAM array and its sense regime

  • US 20090168519A1
  • Filed: 12/31/2007
  • Published: 07/02/2009
  • Est. Priority Date: 12/31/2007
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a plurality of nvDRAM cells;

    a plurality of sense amplifiers; and

    the nvDRAM cells comprising a single data interface, the single data interface coupling the nvDRAM cells to the sense amplifiers, the single data interface operating only at DRAM levels for both volatile and nonvolatile memory operations involving the nvDRAM cells.

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