3T high density NVDRAM cell

• US 20090168520A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Guenther, Stefan, Scade, Andreas
• Granted Patent: US 8,059,458 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

Claims

1-20. -20. (canceled)

21. A memory circuit comprising:

a single transistor storing both volatile and nonvolatile bit charges.

22. The memory circuit of claim 21, wherein the single transistor storing both volatile and nonvolatile bit charges further comprises:

a SONOS transistor.

23. The memory circuit of claim 21, wherein the single transistor storing both volatile and nonvolatile bit charges further comprises:

a Floating-Gate transistor.

24. The memory circuit of claim 21, further comprising:

first and second isolation transistors.

25. The memory circuit of claim 24, wherein the first and second isolation transistors further comprise:

transistors having different gate-oxide thicknesses.

26. The memory circuit of claim 21, further comprising:

a sensing circuit responsive to voltage differentials for volatile operations, and responsive to current flow for at least one nonvolatile operation.

27. The memory circuit of claim 21, further comprising:

a bit cell comprising a pair of charge cells each storing both volatile and nonvolatile bit charges.

28. The memory circuit of claim 27, wherein a single transistor of each charge cell storing both volatile and nonvolatile bit charges further comprises:

a SONOS transistor of each charge cell.

29. The memory circuit of claim 27, further comprising:

a first charge cell of the pair storing both volatile and nonvolatile bit values, and a second charge cell of the pair storing complements of the volatile and nonvolatile bit values.

30. The memory circuit of claim 29, further comprising:

the first charge cell coupled to a bit line and the second charge cell coupled to a complement bit line.

31. The memory circuit of claim 27, wherein each charge cell further comprises:

first and second isolation transistors having different gate-oxide thicknesses.

32. A method of operating a combined volatile and nonvolatile memory circuit, comprising:

causing a first charge representing a nonvolatile bit to be stored in a charge trapping region of a transistor; and

causing a second charge representing a volatile bit to be stored outside the charge trapping region of the transistor.

33. The method of claim 32, further comprising:

detecting the second charge as a voltage disturbance to bit line precharge levels that are approximately halfway between zero and one.

34. The method of claim 32, further comprising:

detecting the first charge via a current flow enabled when the first charge is present and absent otherwise.

35. The method of claim 32, further comprising:

refreshing the second charge from a bit line after a memory operation that affects the first charge.

36. The method of claim 35, further comprising:

refreshing the second charge from the bit line after a volatile memory READ operation that affects the first charge.

37. The method of claim 35, further comprising:

refreshing the second charge from the bit line after a nonvolatile memory ERASE operation that destroys the first charge.

38. The method of claim 35, further comprising:

refreshing the second charge from the bit line after a nonvolatile memory STORE operation that affects the first charge.

39. A device comprising:

a processor coupled to interact with a memory system, the memory system comprising an array of memory cells each storing a single volatile bit and a single nonvolatile bit, each cell employing a single transistor to store the volatile bit and to store the nonvolatile bit.

40. The device of claim 39, further comprising:

the single transistor a SONOS transistor.

41. The device of claim 39, further comprising:

each cell employing a single transistor to store a complement of the volatile bit and to store a complement of the nonvolatile bit.