5T high density NVDRAM cell

• US 20090168521A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Guenther, Stefan, Scade, Andreas
• Granted Patent: US 8,036,032 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Claims

1. A memory circuit comprising:

a high voltage region providing storage of a nonvolatile bit;

a low voltage region providing at least partial storage of a volatile bit; and

the high and low voltage regions isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

2. The memory circuit of claim 1, wherein the high and low voltage regions formed by a plurality of transistors in series further comprises:

the high and low voltage regions formed by five transistors in series between the current source and the bit line.

3. The memory circuit of claim 1, wherein the high and low voltage regions formed by a plurality of transistors in series further comprises:

the high and low voltage regions formed by four transistors in series between the current source and the bit line, and by a capacitor on a branch line.

4. The memory circuit of claim 1, wherein the low voltage region providing at least partial storage of a volatile bit further comprises:

a single transistor of the low voltage region providing substantially all of the volatile bit charge storage via capacitive effects.

5. The memory circuit of claim 4, wherein the single transistor of the low voltage region providing substantially all of the volatile bit charge storage via capacitive effects further comprises:

the single transistor is a depletion mode transistor.

6. The memory circuit of claim 1, wherein the low voltage region providing at least partial storage of a volatile bit further comprises:

the volatile bit storage provided by transistors of both the low and high voltage regions.

7. The memory circuit of claim 6, wherein the volatile bit storage provided by transistors of both the low and high voltage regions further comprises:

a transistor of the high voltage region providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge.

8. The memory circuit of claim 7, wherein the transistor of the high voltage region providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge further comprises:

the transistor providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge is a SONOS transistor.

9. A method of operating a memory circuit, comprising:

causing a high voltage region providing storage of a nonvolatile bit and a low voltage region providing at least partial storage of a volatile bit to become un-isolated from one another so that the value of the volatile bit becomes represented on a bit line;

performing an operation involving the nonvolatile bit that affects the stored value of the volatile bit;

refreshing the stored value of the volatile bit; and

restoring the isolation between the high and low voltage regions.

10. The method of claim 9, further comprising:

operating a SONOS transistor and at least three non-SONOS transistors arranged in series between a current source and a bit line.

11. The method of claim 9, further comprising:

the nonvolatile operation one or more of an ERASE and a STORE.

12. A method of operating a memory circuit to perform a RECALL operation, comprising:

causing a high voltage region providing storage of a nonvolatile bit and a low voltage region providing storage of a volatile bit to become un-isolated from one another;

driving current from the high voltage region through the low voltage region and to a bit line when the stored nonvolatile bit is a one;

storing the value of the bit line to the volatile bit; and

restoring the isolation between the high and low voltage regions.

13. A device comprising:

a processor in communication with a memory system, the memory system comprising memory cells, one or more of the memory cells comprising

a high voltage region providing storage of a nonvolatile bit;

a low voltage region providing at least partial storage of a volatile bit; and

the high and low voltage regions isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

14. The device of claim 13, wherein the high and low voltage regions formed by a plurality of transistors in series further comprises:

the high and low voltage regions formed by five transistors in series between the current source and the bit line.

15. The device of claim 13, wherein the high and low voltage regions formed by a plurality of transistors in series further comprises:

the high and low voltage regions formed by four transistors in series between the current source and the bit line, and by a capacitor on a branch line.

16. The device of claim 13, wherein the low voltage region providing at least partial storage of a volatile bit further comprises:

a single transistor of the low voltage region providing substantially all of the volatile bit charge storage via capacitive effects.

17. The device of claim 16, wherein the single transistor of the low voltage region providing substantially all of the volatile bit charge storage via capacitive effects further comprises:

the single transistor is a depletion mode transistor.

18. The device of claim 13, wherein the low voltage region providing at least partial storage of a volatile bit further comprises:

the volatile bit storage provided by transistors of both the low and high voltage regions.

19. The device of claim 18, wherein the volatile bit storage provided by transistors of both the low and high voltage regions further comprises:

a transistor of the high voltage region providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge.

20. The device of claim 19, wherein the transistor of the high voltage region providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge further comprises:

the transistor providing storage of the nonvolatile bit charge and partial storage of the volatile bit charge is a SONOS transistor.