WEAR LEVEL ESTIMATION IN ANALOG MEMORY CELLS

• US 20090168524A1
• Filed: 12/25/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Sokolov, Dotan, Gurgi, Eyal, Golov, Oren, Winter, Shai, Kasorla, Yoav
• Granted Patent: US 8,085,586 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for operating a memory includes applying at least one pulse to a group of analog memory cells, so as to cause the memory cells in the group to assume respective storage values. After applying the pulse, the respective storage values are read from the memory cells in the group. One or more statistical properties of the read storage values are computed. A wear level of the group of the memory cells is estimated responsively to the statistical properties.

Claims

1. A method for operating a memory, the method comprising:

applying at least one pulse to a group of analog memory cells so as to cause the memory cells in the group to assume respective storage values;

after applying the pulse, reading the respective storage values from the memory cells in the group;

computing one or more statistical properties of the read storage values; and

estimating a wear level of the group of the memory cells responsively to the statistical properties.

2. The method according to claim 1, wherein estimating the wear level comprises estimating a number of Programming and Erasure (P/E) cycles that were previously applied to the group of the memory cells.

3. The method according to claim 1, wherein estimating the wear level comprises predefining a mapping between values of the statistical properties and respective wear levels, and determining the wear level that best matches the computed statistical properties according to the predefined mapping.

4. The method according to claim 1, wherein computing the statistical properties comprises calculating at least one property selected from a group of properties consisting of a mean and a variance of the read storage values.

5. The method according to claim 1, and comprising storing data in the group of the analog memory cells by applying a sequence of Programming and Verification (P&

V) operations to the memory cells in the group, wherein applying the pulse comprises applying a first programming operation in the sequence, and wherein reading the storage values comprises applying a first verification operation in the sequence.

6. The method according to claim 1, wherein estimating the wear level comprises assessing multiple wear levels of multiple respective groups of the memory cells, and comprising allocating at least one of the groups for storage of new data responsively to the assessed wear levels.

7. The method according to claim 1, and comprising setting one or more parameters related to data storage in the group of the memory cells responsively to the estimated wear level.

8. The method according to claim 7, wherein the parameters comprise at least one parameter type selected from a group of types consisting of a read threshold, a verify threshold, an initial pulse amplitude of a sequence of programming pulses that are used for storing data in the memory cells, and an increment between successive programming pulses in the sequence of the programming pulses.

9. The method according to claim 1, and comprising setting a data storage density in the group of the memory cells responsively to the estimated wear level.

10. The method according to claim 9, wherein setting the data storage density comprises selecting at least one property selected from a group of properties consisting of a number of programming levels and an Error Correction Code (ECC) used for data storage in the group.

11. The method according to claim 1, and comprising exchanging a message related to estimation of the wear level over an interface between the memory and a memory controller.

12. The method according to claim 11, wherein exchanging the message comprises sending from the memory controller to the memory a command, which instructs the memory to apply the pulse.

13. The method according to claim 11, wherein exchanging the message comprises reporting the computed statistical properties from the memory to the memory controller.

14. The method according to claim 11, wherein exchanging the message comprises reporting the estimated wear level from the memory to the memory controller.

15. The method according to claim 1, wherein applying the at least one pulse comprises applying one or more erasure pulses so as to cause at least some of the memory cells in the group to assume negative storage values.

16. The method according to claim 15, wherein computing the statistical properties comprises assessing a portion of the memory cells in the group that have assumed the negative storage values responsively to a given number of the erasure pulses.

17. The method according to claim 15, wherein computing the statistical properties comprises counting the erasure pulses needed to cause a given portion of the memory cells in the group to assume the negative storage values.

18. The method according to claim 15, wherein computing the statistical properties comprises comparing the statistical properties before and after applying a given number of the erasure pulses.

19. The method according to claim 15, wherein computing the statistical properties comprises calculating the statistical properties for a subset of the memory cells in the group, which are initially programmed to a given programming level.

20. The method according to claim 15, wherein the memory cells in the group belong to a given word line, and wherein reading the storage values comprises causing at least some of the negative storage values to become positive by programming other memory cells, which belong to one or more word lines that neighbor the given word line.

21. A method for operating a memory, the method comprising:

predefining an action to be applied to one or more groups of analog memory cells in response to respective wear levels of the groups;

applying at least one pulse to a given group of the analog memory cells so as to cause the memory cells in the given group to assume respective storage values;

after applying the pulse, reading the respective storage values from the memory cells in the given group;

computing one or more statistical properties of the read storage values, which are indicative of a wear level of the memory cells in the given group; and

applying the predefined action responsively to the computed statistical properties.

22. Apparatus, comprising:

a memory, which comprises multiple analog memory cells; and

circuitry, which is coupled to apply at least one pulse to a group of the memory cells so as to cause the memory cells in the group to assume respective storage values, to read the respective storage values from the memory cells in the group after applying the pulse, to compute one or more statistical properties of the read storage values, and to estimate a wear level of the group of the memory cells responsively to the statistical properties.

23. The apparatus according to claim 22, wherein the circuitry is coupled to estimate the wear level by estimating a number of Programming and Erasure (P/E) cycles that were previously applied to the group of the memory cells.

24. The apparatus according to claim 22, wherein the circuitry is coupled to hold a predefined mapping between values of the statistical properties and respective wear levels, and to determine the wear level that best matches the computed statistical properties according to the predefined mapping.

25. The apparatus according to claim 22, wherein the circuitry is coupled to calculate at least one statistical property selected from a group of properties consisting of a mean and a variance of the read storage values.

26. The apparatus according to claim 22, wherein the circuitry is coupled to store data in the group of the analog memory cells by applying a sequence of Programming and Verification (P&

V) operations to the memory cells in the group, to use a first programming operation in the sequence for applying the pulse, and to use a first verification operation in the sequence for reading the storage values.

27. The apparatus according to claim 22, wherein the circuitry is coupled to assess multiple wear levels of multiple respective groups of the memory cells, and to allocate at least one of the groups for storage of new data responsively to the assessed wear levels.

28. The apparatus according to claim 22, wherein the circuitry is coupled to set one or more parameters related to data storage in the group of the memory cells responsively to the estimated wear level.

29. The apparatus according to claim 28, wherein the parameters comprise at least one parameter type selected from a group of types consisting of a read threshold, a verify threshold, an initial pulse amplitude of a sequence of programming pulses that are used for storing data in the memory cells, and an increment between successive programming pulses in the sequence of the programming pulses.

30. The apparatus according to claim 22, wherein the circuitry is coupled to set a data storage density in the group of the memory cells responsively to the estimated wear level.

31. The apparatus according to claim 30, wherein the circuitry is coupled to set the data storage density by selecting at least one property selected from a group of properties consisting of a number of programming levels and an Error Correction Code (ECC) used for data storage in the group.

32. The apparatus according to claim 22, wherein the circuitry comprises a Read/Write (R/W) unit that is packaged in a memory device comprising the memory cells, and a memory controller that is separate from the memory device, and wherein the R/W unit and the memory controller are coupled to exchange a message related to estimation of the wear level.

33. The apparatus according to claim 32, wherein the memory controller is coupled to send to the R/W unit a command, which instructs the R/W unit to apply the pulse.

34. The apparatus according to claim 32, wherein the R/W unit is coupled to report the computed statistical properties to the memory controller.

35. The apparatus according to claim 32, wherein the R/W unit is coupled to report the estimated wear level to the memory controller.

36. The apparatus according to claim 22, wherein the at least one pulse comprises one or more erasure pulses, and wherein the circuitry is coupled to apply the erasure pulses so as to cause at least some of the memory cells in the group to assume negative storage values.

37. The apparatus according to claim 36, wherein the circuitry is coupled to assess a portion of the memory cells in the group that have assumed the negative storage values responsively to a given number of the erasure pulses.

38. The apparatus according to claim 36, wherein the circuitry is coupled to count the erasure pulses needed to cause a given portion of the memory cells in the group to assume the negative storage values.

39. The apparatus according to claim 36, wherein the circuitry is coupled to compare the statistical properties before and after applying a given number of the erasure pulses.

40. The apparatus according to claim 36, wherein the circuitry is coupled to calculate the statistical properties for a subset of the memory cells in the group, which are initially programmed to a given programming level.

41. The apparatus according to claim 36, wherein the memory cells in the group belong to a given word line, and wherein the circuitry is coupled to cause at least some of the negative storage values to become positive by programming other memory cells, which belong to one or more word lines that neighbor the given word line.

42. Apparatus, comprising:

a memory, which comprises multiple analog memory cells; and

circuitry, which is coupled to hold a definition of an action to be applied to one or more groups of the memory cells in response to respective wear levels of the groups, to apply at least one pulse to a given group of the memory cells so as to cause the memory cells in the given group to assume respective storage values, to read the respective storage values from the memory cells in the given group after applying the pulse, to compute one or more statistical properties of the read storage values, which are indicative of a wear level of the memory cells in the given group, and to apply the action responsively to the computed statistical properties.

43. Apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple analog memory cells; and

circuitry, which is coupled to apply at least one pulse to a group of the memory cells so as to cause the memory cells in the group to assume respective storage values, to read the respective storage values from the memory cells in the group after applying the pulse, to compute one or more statistical properties of the read storage values, and to estimate a wear level of the group of the memory cells responsively to the statistical properties.

44. Apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple analog memory cells; and

circuitry, which is coupled to hold a definition of an action to be applied to one or more groups of the memory cells in response to respective wear levels of the groups, to apply at least one pulse to a given group of the memory cells so as to cause the memory cells in the given group to assume respective storage values, to read the respective storage values from the memory cells in the given group after applying the pulse, to compute one or more statistical properties of the read storage values, which are indicative of a wear level of the memory cells in the given group, and to apply the action responsively to the computed statistical properties.