Flash memory controller having reduced pinout
First Claim
Patent Images
1. A storage system comprising:
- an integrated circuit device comprising a memory controller, the integrated circuit device including a plurality of pins;
first and second integrated circuit flash memory devices;
the first flash memory device having a first chip select pin and a first ready-busy pin, the second flash memory device having a second chip select pin and a second ready-busy pin;
a signal path connecting the first chip select pin and the first ready-busy pin to a first memory controller pin; and
a signal path connecting the second chip select pin and the second ready-busy pin to a second memory controller pin;
whereby the first memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the first flash memory device and the second memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the second flash memory device.
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Abstract
Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.
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Citations
25 Claims
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1. A storage system comprising:
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an integrated circuit device comprising a memory controller, the integrated circuit device including a plurality of pins; first and second integrated circuit flash memory devices; the first flash memory device having a first chip select pin and a first ready-busy pin, the second flash memory device having a second chip select pin and a second ready-busy pin; a signal path connecting the first chip select pin and the first ready-busy pin to a first memory controller pin; and a signal path connecting the second chip select pin and the second ready-busy pin to a second memory controller pin; whereby the first memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the first flash memory device and the second memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the second flash memory device. - View Dependent Claims (2, 3, 4, 5)
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6. A storage system comprising:
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a storage controller; a first and a second flash memory bank, each made up of a plurality of connected flash memory devices, each flash memory device including a chip select pin and a ready-busy pin; a first signal path connecting the chip select and ready-busy pins of the flash memory devices in the first flash memory bank with a first storage controller pin; a second signal path connecting the chip select and ready-busy pins of the flash memory devices in the second flash memory bank with a second storage controller pin; whereby each signal path is operable in at least two modes, in a first of which the signal path conveys ready-busy information from the ready-busy pins of the flash memory bank to the corresponding controller pin and in a second of which the signal path conveys chip select information from the controller pin to the chip select pins of the corresponding flash memory bank. - View Dependent Claims (7, 8, 9, 10)
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11. A storage system comprising:
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a group of flash memory integrated circuit devices, each flash memory integrated circuit device including; a first flash die and a second flash die; one ready/busy pin per die, each such pin attached to one of the two dice, but not the other; one chip select pin per die, each such pin attached to one of the two dice, but not the other; and a plurality of address, command and/or data pins, each attached to both dice; a storage controller disposed on one or more integrated circuit devices, the storage controller integrated circuit device(s) including a plurality of pins, the pins including; a first storage controller pin directly or indirectly connected to the ready/busy and chip select pins associated with each first flash die, but not connected to the ready/busy pins and chip select pins associated with each second flash die; a second storage controller pin directly or indirectly connected to the ready/busy pins and chip select pins associated with each second flash die, but not connected to the ready/busy pins and chip select pins associated with each first flash die; and a plurality of pins directly or indirectly connected to the plurality of flash memory address, command and/or data pins. - View Dependent Claims (12, 13, 14, 15)
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16. A method of operating a system including a storage controller connected to a group of flash memory devices comprising first and second memory banks, each bank consisting of a plurality of such devices, each of the flash memory devices including a ready/busy pin and a chip select pin, the method comprising the following steps:
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(a) receiving a first ready signal on a first storage controller pin, the first ready signal generated as a result of a ready signal transmitted by the ready/busy pins of each of the flash memory devices in the first memory bank; (b) at least in part in response to receipt of the first ready signal, generating a first chip select signal and transmitting it through the first pin for receipt by chip select pins of each of the first memory bank flash memory devices. - View Dependent Claims (17, 18, 19, 20)
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21. A system including a storage controller and a storage module comprising a plurality of flash memory devices organized into a first and a second memory bank, in which:
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the storage controller includes a first group of pins directly or indirectly connected to the first memory bank and a second group of pins directly or indirectly connected to the second memory bank; the first group of pins including a first pin that in a first mode receives a ready/busy signal generated by anding together signals from a separate ready/busy pin associated with each flash device of the first memory bank, and in a second mode transmits a chip select signal to separate chip select pins associated with each flash device of the first memory bank, the chip select signal being transmitted simultaneously to each of the first memory bank chip select pins; and a first set of pins operable in a first mode to simultaneously transmit the same command to pins of each flash device of the first memory bank, in a second mode to simultaneously transmit the same address to pins of each flash device of the first memory bank and in a third mode to simultaneously transmit data to pins of each flash device of the first memory bank, the data transmitted to each flash device being different; the second group of pins including a second pin that in a first mode receives a ready/busy signal generated by anding together signals from a separate ready-busy pin associated with each flash device of the second memory bank, and in a second mode transmits a chip select signal to separate chip select pins associated with each flash device of the second memory bank, the chip select signal being transmitted simultaneously to each of the second memory bank chip select pins; and a second set of pins operable in a first mode to simultaneously transmit the same command to pins of each flash device of the second memory bank, in a second mode to simultaneously transmit the same address to pins of each flash device of the second memory bank and in a third mode to simultaneously transmit data to pins of each flash device of the second memory bank, the data transmitted to each flash device being different; whereby the first and second group of pins operate independently, such that transmission of any of the described signals on the first group of pins may overlap transmission of any of the described signals on the second group of pins. - View Dependent Claims (22, 23, 24, 25)
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Specification