THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD

• US 20090168533A1
• Filed: 12/24/2008
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Yeong-Taek, PARK, Ki-Tae
• Granted Patent: US 7,924,629 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers.

Claims

1. A method of performing a programming operation within a three-dimensional memory device, the three-dimensional memory device comprising a stacked plurality of layers, each layer comprising a memory array, and each memory array comprising a string of memory cells, the method comprising:

for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage; and

thereafter,

programming a selected string associated with a selected layer in the plurality of layers.

2. The method of claim 1, wherein the shut-off voltage is equal to a voltage greater than or equal to a power supply voltage less a threshold voltage for a ground selection transistor disposed in an unselected layer.

3. The method of claim 2, wherein respective strings associated with each one of the plurality of layers are commonly connected to a shared bit line.

4. The method of claim 3, wherein respective strings associated with each one of the plurality of layers are commonly connected to a single common source line.

5. The method of claim 4, wherein the programming operation further comprises applying the power supply voltage to the common source line.

6. The method of claim 5, wherein the programming operation further comprises:

applying the power source voltage to a selected string selection line associated with the selected layer, and applying a ground voltage of a selected ground selection line associated with the selected layer, and

applying the ground voltage to unselected string selection lines associated with unselected layers, and applying the power supply voltage to unselected ground selection lines associated with the unselected layers.

7. The method of claim 6, further comprising:

after charging the channel of memory cells associated with unselected strings, initially applying a pass voltage to a selected word line associated with a memory cell to be programmed and to unselected word lines not associated with the memory cell to be programmed; and

thereafter,

increasing the pass voltage applied to the selected word line.

8. The method of claim 7, wherein the pass voltage applied to the selected word line is increased by a programming voltage.

9. The method of claim 7, wherein initially applying the pass voltage to the selected and unselected word lines generates an elevated channel voltage for channels of memory cells associated with unselected strings.

10. The method of claim 3, wherein respective strings associated with each one of the plurality of layers are respectively connected to one of a plurality of layer specific common source lines.

11. The method of claim 10, wherein the programming operation further comprises:

applying the power supply voltage to a selected common source line in the plurality of common source lines associated with the selected layer; and

applying an elevated voltage higher than the power supply voltage to unselected common source lines in the plurality of common source lines associated with the unselected layers.

12. The method of claim 11, wherein the programming operation further comprises:

applying the power source voltage to a selected string selection line associated with the selected layer, and applying a ground voltage of a selected ground selection line associated with the selected layer, and

applying the ground voltage to unselected string selection lines associated with unselected layers, and applying the power supply voltage to unselected ground selection lines associated with the unselected layers.

13. The method of claim 12, further comprising:

after charging the channel of memory cells associated with unselected strings, initially applying a pass voltage to a selected word line associated with a memory cell to be programmed and to unselected word lines not associated with the memory cell to be programmed; and

thereafter,

increasing the pass voltage applied to the selected word line.

14. The method of claim 13, wherein the pass voltage applied to the selected word line is increased by a programming voltage.

15. The method of claim 14, wherein initially applying the pass voltage to the selected and unselected word lines generates an elevated channel voltage for channels of memory cells associated with unselected strings.

16. A memory system comprising a memory controller and a three-dimensional memory device;

wherein the three-dimensional memory device comprises;

a stacked plurality of layers, each layer comprising a memory array having a string of memory cells, wherein programming data to a memory cell of a respective string is controlled by a selection transistor and a ground selection transistor associated with the string;

a plurality of shared word lines configured to program data to memory cells in strings associated with each one of the plurality of layers;

a shared bit line configured to program data to memory cells in strings associated with each one of the plurality of layers; and

the memory controller configured to receive an address defining a selected layer from the plurality of layers containing a memory cell to be programmed and unselected layers, and thereafter charging the channel of memory cells in strings associated with the unselected layers with a shut-off voltage, and thereafter programming a memory cell of a string associated with a selected layer.

17. The memory system of claim 16, further comprising:

a single common source line commonly connected to strings in each one of the plurality of layers and configured to program data to the memory cell of the string associated with the selected layer.

18. The memory system of claim 16, further comprising:

a plurality of common source lines respectively connected to a string associated with one of the plurality of layers and configured to program data to the memory cell of the string when the one of the plurality of layers is the selected layer.