THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE
First Claim
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1. A 3D memory device comprising:
- a first plane including a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line; and
a second plane including a second mat formed on the first layer and a fourth mat formed on the second layer, the second and fourth mats sharing a bit line, wherein each one of the first through fourth mats comprises a plurality of blocks, wherein a block associated with the first plane is simultaneously accessed with a block of the second plane.
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Abstract
Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.
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Citations
18 Claims
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1. A 3D memory device comprising:
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a first plane including a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line; and a second plane including a second mat formed on the first layer and a fourth mat formed on the second layer, the second and fourth mats sharing a bit line, wherein each one of the first through fourth mats comprises a plurality of blocks, wherein a block associated with the first plane is simultaneously accessed with a block of the second plane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A 3D memory device comprising:
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a bit line; first and second NAND strings connected to the bit line; and a page buffer configured to perform an erase-verification operation in relation to the first NAND string by determining whether the bit line is charged following an erase operation applied to the first NAND string, and further configured to perform the erase-verification operation in relation to the second NAND string by determining whether the bit line is discharged following an erase operation applied to the second NAND string. - View Dependent Claims (16, 17)
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18. A multi-plane operation method for a 3D memory device, comprising:
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inputting an operation command; inputting an address of a first plane; inputting an address of a second plane; and conducting a multi-plane operation in response to the operation command, wherein the addresses of the first and second planes are different from each other in block address.
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Specification