POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES

• US 20090168843A1
• Filed: 10/02/2008
• Published: 07/02/2009
• Est. Priority Date: 10/03/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ramasubramanian, Karthik, Raghupathy, Arun, Waters, Deric Wayne
• Granted Patent: US 8,331,898 B2
• Time in Patent Office: Days
• US Class Current: 375/130
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34

Abstract

An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (T_ON, T_OFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Claims

13. A power management circuit for controlling a process having a maximum available interval for coherent summations, the power management circuit comprising

a power gating circuit operable to turn power on and off to at least one portion of the process;

and

a control circuit operable to establish a rate of turning the power on and off by said power gating circuit so that the rate equals or exceeds the reciprocal of the maximum available interval for coherent summations.

1. An electronic circuit comprising

a receiver circuit operable to perform coherent summations having a coherent summations time interval;

and

a power control circuit coupled to said receiver circuit and operable to impress a power controlling duty cycle on the receiver circuit inside the coherent summations time interval.

2. The electronic circuit claimed in claim 1 wherein said receiver circuit also is operable to perform non-coherent summations of the coherent summations and said power control circuit is concurrently operable to impress a power management control longer than the coherent summations time interval, on both the coherent summations and the non-coherent summations.

3. The electronic circuit claimed in claim 1 wherein said receiver circuit also is operable to perform non-coherent summations of the coherent summations and the noncoherent summations have a non-coherent summations period and said power control circuit is operable to impress a power management control on the non-coherent summations during multiple intervals in the non-coherent summations period.

4. The electronic circuit claimed in claim 3 wherein said power control circuit is dynamically operable to determine the number of the multiple intervals as a function of Doppler difference over time.

5. The electronic circuit claimed in claim 1 wherein said power control circuit is dynamically operable to determine the duty cycle inside the coherent summations time interval as a function of a signal to noise ratio (SNR).

6. The electronic circuit claimed in claim 5 wherein the duty cycle has a power-off time that stepwise increases with SNR.

7. The electronic circuit claimed in claim 1 wherein said power control circuit determines the duty cycle by a process including rank ordering a plurality of signals by their signal to noise ratios.

8. The electronic circuit claimed in claim 1 operable with a number of received signals wherein said power control circuit is operable to dynamically control said receiver circuit to extract a fewer number of the received signals.

9. The electronic circuit claimed in claim 8 wherein said power control circuit is operable to select the fewer number of received signals based on a dilution of precision test relative to a dilution of precision threshold.

10. The electronic circuit claimed in claim 1 wherein said receiver circuit includes an accumulate and dump circuit.

11. The electronic circuit claimed in claim 1 wherein said receiver circuit includes a despreading circuit operable to despread at least one spread spectrum signal.

12. If the electronic circuit claimed in claim 1 wherein said receiver circuit is selected from the group consisting of 1) receiver circuit for satellite signals, 2) cellular receiver circuit, 3) MIMO receiver circuit, 4) wireless local area network receiver circuit, 5) wireless gateway circuit, 6) base station circuit, 7) medical communication circuit.

14. The power management circuit claimed in claim 13 wherein said power gating circuit is configurable and said control circuit is operable to configure said power gating circuit.

15. The power management circuit claimed in claim 14 wherein power is gated by at least part of said power gating circuit to said control circuit itself.

16. The power management circuit claimed in claim 13 wherein said control circuit is further operable to establish an on-time interval for said power gating circuit at the established rate.

17. The power management circuit claimed in claim 13 further comprising a voltage supply circuit operable to regulate power to said power gating circuit.

18. The power management circuit claimed in claim 13 wherein said control circuit has an input for at least one signal representing signal-to-noise ratio.

19. The power management circuit claimed in claim 13 wherein said control circuit has an input for at least one signal representing user application information.

20. The power management circuit claimed in claim 13 wherein said control circuit has an input for at least one signal representing Doppler difference.

21. The power management circuit claimed in claim 13 wherein said control circuit has an output for providing a signal representing a selected power save mode.

22. The power management circuit claimed in claim 13 wherein said control circuit has an output coupled to said power gating circuit for a power control signal at the established rate, and said control circuit is operable to turn the power control signal itself on and off at a second rate that is less than half the established rate of the power control signal.

23. The power management circuit claimed in claim 22 wherein said control circuit has an input for at least one signal representing Doppler difference and said control circuit is operable to adjust the second rate as a function of the Doppler difference.

24. The power management circuit claimed in claim 22 for use with a process also having noncoherent summations wherein said power gating circuit is responsive to said control circuit to gate power for the noncoherent summations at the second rate.

25. The power management circuit claimed in claim 13 wherein said control circuit includes a counter circuit feeding a decoder circuit.

26. The power management circuit claimed in claim 13 for use with the process having channels wherein said power control circuit is operable to change a number of channels to be powered, and said power gating circuit is responsive to said power control circuit to gate power to the channels to be powered.

27. The power management circuit claimed in claim 13 wherein the process has plural portions and said power gating circuit is operable to turn power on and off to different portions at different times.

28. The power management circuit claimed in claim 13 wherein said control circuit is operable to enable the power control signal with an adjustable enable time that is at least twice the duration of the period of the established rate of the power control signal.

29. The power management circuit claimed in claim 28 wherein said control circuit has an input for a signal representative of a data decoding mode and said control circuit has a bypass to provide a continual enable for the power control signal during data decoding for the established rate to continue.

30. The power management circuit claimed in claim 13 wherein said control circuit has at least one input for signals representing a plurality of signal-to-noise ratios and said control circuit determines an off-time for the power control signal as a generally increasing function of at least one of the signal-to-noise ratios.

31. The power management circuit claimed in claim 13 wherein said control circuit has at least one input for signals representing a plurality of signal-to-noise ratios (SNRs) and said control circuit determines a duty cycle for the power control signal substantially according to the relationship 10̂

(−

SNR_extra/10), where extra signal-to-noise ratio SNR_extra is in decibels (dB).

32. The power management circuit claimed in claim 13 wherein the process has symbol periods that are delayed relative to each other for the coherent summations in different channels.

25-1. The power management circuit claimed in claim 13 for use with an RF front-end process wherein said power gating circuit has a portion having a gated power output for the RF front-end process.

33. A method of operating a receiver circuit having coherent summations during a coherent summations time interval, the method comprising impressing a power controlling duty cycle on the receiver circuit inside the coherent summations time interval.

34. The method claimed in claim 33 wherein said impressing includes turning power on and off at a rate that equals or exceeds the reciprocal of the coherent summations time interval.

35. A telecommunications device comprising

a spread spectrum receiver circuit operable to perform coherent summations having a coherent summations time interval;

and

a power control circuit coupled to said receiver circuit and operable to impress a power controlling duty cycle on the spread spectrum receiver circuit inside the coherent summations time interval.

36. The telecommunications device claimed in claim 35 further comprising a position display unit coupled to said spread spectrum receiver circuit and wherein said spread spectrum receiver circuit includes a wireless communications receiving section also coupled to said power control circuit.

37. The telecommunications device claimed in claim 35 wherein said spread spectrum receiver circuit includes multiple channels for receiving satellite signals, and said power control circuit is coupled to control how many of the multiple channels are active.

38. The telecommunications device claimed in claim 35 wherein said spread spectrum receiver circuit includes multiple channels for receiving satellite signals and a processor circuit for executing an application selected from the group comprising 1) position sensing, 2) user kinematics, 3) phase tracking, 4) satellite data decoding, 5) Doppler tracking, 6) attitude sensing, 7) Doppler difference tracking.

39. The telecommunications device claimed in claim 35 wherein said spread spectrum receiver circuit includes a processing circuit and the device further comprises an accelerometer coupled with said processing circuit.

40. The telecommunications device claimed in claim 35 further comprising a cellular communications circuit and wherein said power control circuit is also operable to put said spread spectrum receiver asleep for a period of time, and said cellular communications circuit is operable to perform timekeeping at least when said spread spectrum receiver is asleep and to provide a time update when said spread spectrum receiver wakes up.

41. The electronic circuit claimed in claim 35 wherein said spread spectrum receiver circuit also is operable to perform non-coherent summations of the coherent summations and said power control circuit is concurrently operable to impress a power management control longer than the coherent summations time interval, on both the coherent summations and the non-coherent summations.

42. A process of manufacturing comprising fabricating as an integrated circuit on a wafer a receiver circuit for coherent summations having a coherent summations time interval and a power control circuit to impress a power controlling duty cycle on the receiver circuit inside the coherent summations time interval.