Etch residue reduction by ash methodology

• US 20090170221A1
• Filed: 12/28/2007
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ramappa, Deepak A., Jacques, Jeannette Michelle
• Granted Patent: US 7,910,477 B2
• Time in Patent Office: Days
• US Class Current: 438/6
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Abstract

Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Claims

1. A method of forming a dual damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer to provide electrical coupling to a conductive feature in an existing interconnect structure, the method comprising:

forming an etch stop layer over the existing interconnect structure;

forming a dielectric layer over the etch-stop layer;

forming a via cavity in the dielectric layer over the etch stop layer;

forming a trench cavity in the dielectric layer;

performing an ashing operation to remove polymer residue; and

extending the via cavity through a portion of the etch stop layer to expose the conductive feature in the existing interconnect structure.

2. The method of claim 1, wherein the dielectric layer comprises an ultra low-k dielectric material.

3. The method of claim 1, wherein the ashing operation comprises a first ash operation and a second ash operation.

4. The method of claim 3, wherein the first ashing operation is performed at a chamber pressure of from about 10 mTorr to about 300 mTorr and a flow rate of process gas of from about 1-sccm to about 4000 sccm.

5. The method of claim 4, wherein the process gas comprises one or more of C, CO, CO₂, H₂, NH₃, He, Ar and/or N₂.

6. The method of claim 3, wherein the endpoint of the first ashing operation is determined by one or more methods of endpoint detection.

7. The method of claim 6, wherein the methods of endpoint detection comprise monitoring of a chemical component or monitoring of emission of light from the process gas.

8. The method of claim 3, wherein the second operation comprises an overash in an amount from about 50% to about 500%.

9. The method of claim 1, wherein forming the via cavity through the portion of the dielectric layer comprises etching the portion of the dielectric layer to form the via cavity to expose the portion of the etch-stop layer using a via etch process, and wherein extending the via cavity through the portion of the etch-stop layer comprises etching an exposed portion of the etch-stop layer to expose the conductive feature in the exiting interconnect structure using an etch-stop process.

10. The method of claim 6, wherein the ashing operation is performed prior to the etch-stop etch process.

11. The method of claim 1, further comprising forming a cap layer over the dielectric layer.

12. The method of claim 1, further comprising filling the cavity with a conductive material.

13. A method for the removal of residue from a cavity during formation of a dual damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer to provide electrical coupling to a conductive feature in an existing interconnect structure, the method comprising:

forming an etch stop layer over the existing interconnect structure;

forming a dielectric layer over the etch-stop layer;

forming a via cavity in the dielectric layer over the etch stop layer;

forming a trench cavity in the dielectric layer;

performing an ashing operation to remove polymer residue; and

extending the via cavity through a portion of the etch stop layer to expose the conductive feature in the existing interconnect structure.

14. The method of claim 13, wherein the ashing operation comprises a first ash operation and a second ash operation.

15. The method of claim 14 wherein the ashing operation is performed at a chamber pressure of from about 10 mTorr to about 300 mTorr, a flow rate of process gas of from about 10 sccm to about 4000 sccm, and a power ranging from about 200 watts to about 2000 watts.

16. The method of claim 15, wherein the process gas comprises one or more of C, CO, CO₂, H₂, NH₃, He, Ar and/or N₂.

17. The method of claim 13, wherein the endpoint of the first ashing operation is determined by one or more methods of endpoint detection.

18. The method of claim 17, wherein the methods of endpoint detection comprise monitoring of a chemical component or monitoring of emission of light from the process gas.

19. The method of claim 13, wherein the ashing operation is performed prior to the etch-stop etch process.

20. A method for manufacturing an integrated circuit, comprising:

providing a semiconductor wafer having a dual damascene interconnect structure overlying an existing interconnect structure thereon, including;

forming an etch stop layer over the interconnect structure;

forming a dielectric layer over the etch-stop layer;

forming a via cavity in the dielectric layer over the etch stop layer;

forming a trench cavity in the dielectric layer;

performing an ashing operation to remove polymer residue; and

extending the via cavity through a portion of the etch stop layer to expose the conductive feature in the existing interconnect structure.