METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR
First Claim
1. A method for manufacturing a semiconductor device having a vertical transistor, comprising the steps of:
- forming hard masks on a semiconductor substrate such that portions of the semiconductor substrate are exposed;
etching the exposed portions of the semiconductor substrate to define grooves therein;
forming a gate conductive layer on the hard masks and surfaces of the grooves to a thickness, wherein the gate conductive layer does not fill the grooves;
forming a sacrificial layer on the gate conductive layer to fill the grooves;
removing a partial thickness of the sacrificial layer to expose the gate conductive layer;
removing a portion of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves;
removing the remaining sacrificial layer; and
forming gates on sidewalls of lower portions of the grooves by selectively etching the gate conductive layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
21 Citations
20 Claims
-
1. A method for manufacturing a semiconductor device having a vertical transistor, comprising the steps of:
-
forming hard masks on a semiconductor substrate such that portions of the semiconductor substrate are exposed; etching the exposed portions of the semiconductor substrate to define grooves therein; forming a gate conductive layer on the hard masks and surfaces of the grooves to a thickness, wherein the gate conductive layer does not fill the grooves; forming a sacrificial layer on the gate conductive layer to fill the grooves; removing a partial thickness of the sacrificial layer to expose the gate conductive layer; removing a portion of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves; removing the remaining sacrificial layer; and forming gates on sidewalls of lower portions of the grooves by selectively etching the gate conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification