COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE

• US 20090172213A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Faber, Robert W., Jayachandran, Sowmiya, Khan, Jawad B., Webb, Randall K.
• Application Number:
  US11/968,042
• Publication Number:
  US 20090172213A1
• Time in Patent Office: Days
• US Class Current: 710/19
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.

Claims

1. A method comprising:

waiting a hold off time after a memory command has issued; and

after the hold off time has elapsed following the issuance of the memory command, performing a status read operation to determine a status of the memory command.

2. The method of claim 1, further comprising:

if the status read operation indicates that the memory command has not been completed, then waiting a polling interval after performing the status read operation;

after the polling interval has elapsed, then performing another status read operation to determine the status of the memory command; and

if the status read operation performed after waiting for the polling interval indicates that the memory command has not been completed, repeating waiting the polling interval before performing another status read operation each time until receiving an indication that the memory command has been completed.

3. The method of claim 1, wherein the hold off time varies depending on the type of the memory command.

4. The method of claim 1, further comprising updating the hold off time.

5. The method of claim 4, wherein the updating is dependent on changing average memory command completion times.

6. The method of claim 2, wherein the hold off time and the polling interval vary depending on the type of the NAND command.

7. The method of claim 2, further comprising updating the hold off time and/or the polling interval.

8. The method of claim 7, wherein the updating is dependent on changing average memory command completion times.

9. An apparatus comprising:

one or more memory devices; and

a controller to wait a hold off time after a memory command has issued for the memory, and after the hold off time has elapsed following the issuance of the memory command, to perform a status read operation to determine a status of the memory command.

10. The apparatus of claim 9, the controller further to wait a polling interval after the performing of the status command operation if the status read operation indicates that the memory command has not been completed, to perform another status read operation to determine the status of the memory command after the polling interval has elapsed, and to repeat waiting the polling interval before performing another status read operation each time if the status read operation performed after waiting for the polling interval indicates that the memory command has not been completed, the repeating to continue until receiving an indication that the memory command has been completed.

11. The apparatus of claim 9, wherein the hold off time varies depending on the type of the memory command.

12. The apparatus of claim 9, the controller to update the hold off time.

13. The apparatus of claim 12, the controller to update the hold off time in response to changing average memory command completion times.

14. The apparatus of claim 10, wherein the hold off time and the polling interval vary depending on the type of the memory command.

15. The apparatus of claim 10, the controller to update the hold off time and/or the polling interval.

16. The apparatus of claim 14, wherein the updating is dependent on changing average memory command completion times.

17. A method comprising:

waiting a polling interval at some point after a memory command has issued;

after the polling interval has elapsed, then performing a status read operation to determine the status of the memory command; and

if the status command operation performed after waiting for the polling interval indicates that the memory command has not been completed, repeating waiting the polling interval before performing another status read operation each time until receiving an indication that the memory command has been completed.

18. The method of claim 17, further comprising updating the polling interval.

19. The method of claim 18, wherein the updating is dependent on changing average memory command completion times.

20. The method of claim 17, wherein the polling interval varies depending on the type of the memory command.

21. An apparatus comprising:

one or more memory devices; and

a controller to wait a polling interval at some point after a memory command has issued for the memory, and after the polling interval has elapsed, to perform a status read operation to determine a status of the memory command, and to repeat waiting the polling interval before performing another status read operation each time until receiving an indication that the memory command has been completed.

22. The apparatus of claim 21, the controller further to update the polling interval.

23. The apparatus of claim 21, the controller further to update the polling interval in a manner that is dependent on changing average memory command completion times.

24. The apparatus of claim 21, the controller further to vary the polling interval depending on the type of the memory command.