SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE

• US 20090172227A1
• Filed: 12/27/2007
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: IGT (International Game Technology)
• Original Assignee: IGT (International Game Technology)
• Inventors: Taylor, Eric, Leary, Tina, Stockdale, James
• Granted Patent: US 8,140,796 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 21/80 in storage media based on magnetic or optical technology, e.g. disks with sectors preventing unauthorised reproduction or copying of disc-type recordable media G11B20/00

Abstract

A mass storage device protection system may have a mass storage device, a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link, and a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following: intercept the at least one serial write command signal, and determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal.

Claims

1. A mass storage device protection system, comprising:

a mass storage device;

a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link; and

a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following;

intercept the at least one serial write command signal; and

determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal.

2. The system of claim 1, wherein the storage protector comprises a logic device configured to do the following:

replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal,

transmit the first serial write command signal to the mass storage device;

de-serialize the second serial write command signal; and

interpret the de-serialized write command signal using a comparator module.

3. The system of claim 1, wherein the storage protector is configured to transmit a fault signal to the mass storage device and processor when it is determined that the at least one serial write command signal comprises an unauthorized command signal.

4. The system of claim 1, further comprising an interface configured for communication with one or more external devices, wherein the storage protector is further configured to enable or disable write commands to the mass storage device according to instructions received from an external device.

5. The system of claim 1, wherein the storage protector comprises:

a bus flow controller configured to replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal, the first serial write command signal transmitted to the mass storage device;

a translator configured for communication with the bus flow controller and configured to de-serialize the second serial write command signal; and

a comparator module configured for communication with the translator, the comparator module configured to interpret the de-serialized write command signal.

6. The system of claim 2, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

7. The system of claim 5, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

8. The system of claim 6, wherein the issued command comprises an invalid command and wherein the at least one reply is a non-maskable interrupt or a reset signal.

9. The system of claim 6, wherein the issued command comprises a valid command signal transmitted to the processor.

10. The system of claim 7, wherein the issued command comprises an invalid command and wherein the at least one reply comprises a non-maskable interrupt or a reset signal transmitted to the processor.

11. The system of claim 7, wherein the issued command comprises a valid command signal transmitted to the processor.

12. The system of claim 7, wherein the register further comprises information specifying whether mass storage device protection is activated.

13. A gaming machine, comprising:

a cabinet to house a plurality of gaming machine components;

a control system housed within the cabinet, comprising;

a mass storage device;

a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link; and

a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following;

intercept the at least one serial write command signal; and

determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal;

means for providing a wagering game; and

means for receiving a wager to play the wagering game.

14. The gaming machine of claim 13, wherein the storage protector comprises a logic device configured to do the following:

replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal,

transmit the first serial write command signal to the mass storage device;

de-serialize the second serial write command signal; and

interpret the de-serialized write command signal using a comparator module.

15. The gaming machine of claim 13, wherein the storage protector is configured to transmit a fault signal to the mass storage device and processor when it is determined that the at least one serial write command signal comprises an unauthorized command signal.

16. The gaming machine of claim 13, wherein the storage protector is configured for communication with one or more external devices, wherein the storage protector is further configured to enable or disable write commands to the mass storage device according to instructions received from an external device.

17. The gaming machine of claim 13, wherein the storage protector comprises:

a bus flow controller configured to replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal, the first serial write command signal transmitted to the mass storage device;

a translator configured for communication with the bus flow controller and configured to de-serialize the second serial write command signal; and

a comparator module configured for communication with the translator, the comparator module configured to interpret the de-serialized write command signal.

18. The gaming machine of claim 14, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

19. The gaming machine of claim 17, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

20. The gaming machine of claim 18, wherein the issued command comprises an invalid command and wherein the at least one reply is a non-maskable interrupt or a reset signal.

21. The gaming machine of claim 18, wherein the issued command comprises a valid command signal transmitted to the processor.

22. The gaming machine of claim 19, wherein the issued command comprises an invalid command and wherein the at least one reply comprises a non-maskable interrupt or a reset signal transmitted to the processor.

23. The gaming machine of claim 19, wherein the issued command comprises a valid command signal transmitted to the processor.

24. The gaming machine of claim 19, wherein the register further comprises information specifying whether mass storage device protection is activated.

25. A method for protecting a mass storage device, comprising:

receiving a serial write command to the mass storage device via a serial communication link;

intercepting the at least one serial write command by a storage protector;

replicating the at least one serial write command to form a first serial write command signal and a second serial write command signal;

transmitting the first serial write command signal to the mass storage device;

comparing the second write command signal to a user write command in a register; and

determining whether the second write command signal matches the user write command.

26. The method of claim 25, further comprising transmitting a reset signal, fault signal, or a non-maskable interrupt from the storage protector to the processor and mass storage device when it is determined that the second write command signal matches the user write command.

27. The method of claim 26, further comprising resetting the mass storage device and processor after a predetermined time period.

28. The method of claim 25, further comprising receiving instructions from a remote device to open or close the serial communication link to the mass storage device.

29. The method of claim 25, further comprising receiving information specifying whether mass storage device protection is activated.

30. A mass storage device protection system, comprising:

a mass storage device; and

a controller configured for communication with the mass storage device, the controller having;

a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link; and

a storage protector configured for communication with the processor to determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal.

31. The system of claim 30, wherein the storage protector comprises a logic device configured to do the following:

replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal,

transmit the first serial write command signal to the mass storage device;

de-serialize the second serial write command signal; and

interpret the de-serialized write command signal using a comparator module

32. The system of claim 30, wherein the storage protector is configured to transmit a fault signal to the mass storage device and processor when it is determined that the at least one serial write command signal comprises an unauthorized command signal.

33. The system of claim 30, further comprising an interface configured for communication with one or more external devices, wherein the storage protector is further configured to enable or disable write commands to the mass storage device according to instructions received from an external device.

34. The system of claim 30, wherein the storage protector comprises:

a bus flow controller configured to replicate the at least one serial write command signal to generate a first serial write command signal and a second serial write command signal, the first serial write command signal transmitted to the mass storage device;

a translator configured for communication with the bus flow controller and configured to de-serialize the second serial write command signal; and

a comparator module configured for communication with the translator, the comparator module configured to interpret the de-serialized write command signal.

35. The system of claim 31, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

36. The system of claim 34, wherein the comparator module comprises:

a command latch for storing commands from the storage protector;

a register having a fixed command array to store a plurality of user write commands; and

a comparator configured for communication with the command latch and the register, wherein the comparator is configured to issue a command when the command latch stores a user write command matching at least one of the plurality of user write commands.

37. The system of claim 35, wherein the issued command comprises an invalid command and wherein the at least one reply is a non-maskable interrupt or a reset signal.

38. The system of claim 35, wherein the issued command comprises a valid command signal transmitted to the processor.

39. The system of claim 36, wherein the issued command comprises an invalid command and wherein the at least one reply comprises a non-maskable interrupt or a reset signal transmitted to the processor.

40. The system of claim 36, wherein the issued command comprises a valid command signal transmitted to the processor.

41. The system of claim 36, wherein the register further comprises information specifying whether mass storage device protection is activated.