Multiprocessor storage controller
First Claim
Patent Images
1. A storage system comprising:
- first and second flash memory groups, each group consisting of a plurality of flash memory devices;
a storage controller disposed on a single integrated circuit device, the storage controller including a plurality of groups of processors, each processor group consisting of one or more processors handling a different stage of a pipelined execution of host storage commands, the processor groups including;
a first processor group including a first processor associated with the first flash memory group and a second processor associated with the second flash memory group, each such processor controlling at least some operations of the corresponding flash memory group;
whereby the first flash memory group is capable of carrying out flash read or write operations relating to a first host command at the same time that the second flash memory group carries out flash read or write operations relating to a second host command.
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Abstract
A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.
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Citations
25 Claims
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1. A storage system comprising:
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first and second flash memory groups, each group consisting of a plurality of flash memory devices; a storage controller disposed on a single integrated circuit device, the storage controller including a plurality of groups of processors, each processor group consisting of one or more processors handling a different stage of a pipelined execution of host storage commands, the processor groups including; a first processor group including a first processor associated with the first flash memory group and a second processor associated with the second flash memory group, each such processor controlling at least some operations of the corresponding flash memory group; whereby the first flash memory group is capable of carrying out flash read or write operations relating to a first host command at the same time that the second flash memory group carries out flash read or write operations relating to a second host command. - View Dependent Claims (2, 3, 4, 5)
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6. A method of operating a system including a storage controller disposed on a single integrated circuit device, and a plurality of groups of flash memory devices, the storage controller including a first processor group, a second processor group and a third processor group, each processor group made up of at least one processor, the method comprising the following steps:
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(a) receiving a first host command from a first host at a first processor, the first processor being part of the first processor group, the first host command including a first logical address or range; (b) the first processor performing a task related to the first host command; (c) the first processor directly or indirectly passing information related to the first host command to a second processor, the second processor being part of the second processor group, (d) the second processor evaluating the first logical address or range; (e) based at least in part on the first logical address or range, the second processor directly or indirectly passing information related to the first host command to a third processor, the third processor being part of the third processor group; (f) the third processor initiating a flash memory read in a first flash group, based at least in part on information directly or indirectly received from the second processor. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of operating a storage system comprising the following steps:
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(a) at a first host port, receiving a first communication from a first host including a first host command; (b) a first processor performing an action relating to the first host command; (c) transmitting information relating to the first host command to a second processor; (d) the second processor evaluating the first host command, (e) the second processor routing information relating to the first host command based at least in part on the evaluation; (f) receiving information related to the first host command at a third processor; (g) at the third processor, evaluating a first logical address associated with the first host command; (h) based at least in part on the first logical address;
routing information relating to the first host command to a fourth processor;(i) at the fourth processor, evaluating the received information relating to the first host command; (j) at the fourth processor, generating a first flash read command based on the first host command; (k) communicating the first flash read command to a first flash group; (l) the first flash group executing the first flash read command; (m) communicating information relating to the status of the first flash read command to the fourth processor; (n) following completion of the first flash read command, communicating information relating to the first flash read command to a fifth processor; (o) the fifth processor taking an action relating to formatting the information read in the first flash read command for transmission to a host; (p) transmitting the information read in the first flash read command to the first host through the first host port. - View Dependent Claims (17, 18, 19, 20)
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21. A method of operating a storage system including the following steps:
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(a) a first processor receiving first information relating to a first host command; (b) based at least in part on such information, the first processor generating a first flash command and a second flash command; (c) the first processor transmitting the first flash command to a first flash memory group consisting of a plurality of flash memory devices; (d) the first flash memory group carrying out a first flash operation based on the first flash command; (e) the first processor transmitting the second flash command to the first flash memory group, the second command being transmitted to the first flash memory group prior to completion of the first flash operation; (f) the first flash memory group carrying out a second flash operation based on the second flash command; (g) a second processor receiving second information relating to a second host command (h) based at least in part on such information, the second processor generating a third flash command and a fourth flash command; (i) the second processor transmitting the third flash command to a second flash memory group consisting of a plurality of flash memory devices; (j) the second flash memory group carrying out a third flash operation based on the third flash command; (k) the second processor transmitting the fourth flash command to the second flash memory group, the fourth command being transmitted to the second flash memory group prior to completion of the third flash operation; (l) the second flash memory group carrying out a fourth flash operation based on the fourth flash command whereby the storage system executes multiple flash commands relating to multiple host commands in an overlapped manner. - View Dependent Claims (22, 23, 24, 25)
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Specification