Obscuring Memory Access Patterns in Conjunction with Deadlock Detection or Avoidance

• US 20090172304A1
• Filed: 12/28/2007
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sheaffer, Gad, Gueron, Shay, Raikin, Shlomo
• Granted Patent: US 8,407,425 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

Claims

1. A computer-implemented method comprising:

loading data into locations of a memory resource and executing one or more monitor instruction for the locations;

reading the data from the memory structure, in a pre-specified order, responsive to determining that the data at one or more of the locations has been accessed by another thread;

wherein said determining further comprises polling of a status bit to determine whether the data at any of the data has been accessed by the other thread.

2. The method of claim 1, further comprising:

reading only a portion of the data from the memory structure, responsive to determining that the data at the locations remains unmodified.

3. The method of claim 1, wherein:

said memory resource further comprises a local cache.

4. The method of claim 1, wherein:

said polling is performed via execution of an architectural instruction.

5. The method of claim 1, wherein:

said status bit is part of a status register that may be read via execution of an architectural instruction.

6. The method of claim 1, wherein said one or more monitor instruction further comprises:

an architectural instruction to set the status bit responsive to a foreign write to one or more of the monitored locations.

7. The method of claim 1, wherein said one or more monitor instruction further comprises:

an architectural instruction to set the status bit responsive to eviction of one or more of the monitored locations

8. A computer-implemented method, comprising:

executing via a first thread one or more instructions to register a handler module to be invoked in response to an access, via a second thread, to one or more specified memory locations;

transferring control to the handler module in response to an access, via the second thread, to one or more of the specified memory locations;

incrementing a counter; and

executing a deadlock policy responsive to the counter exceeding a maximum acceptable value.

9. The method of claim 8, wherein incrementing a counter further comprises:

incrementing the counter responsive to each control transfer to the handler module.

10. The method of claim 8, wherein:

the counter is one of a plurality of counters, each counter being associated with a different instruction of the first thread; and

the counter is incremented responsive to determining that the handler module has been invoked from the instruction of the first thread.

11. The method of claim 8, wherein:

executing the deadlock policy further comprises aborting execution of the first thread.

12. The method of claim 8, wherein:

executing the deadlock policy further comprises presenting a message to a user.

13. The method of claim 8, further comprising:

returning control from the handler to the first thread.

14. The method of claim 13, further comprising:

loading data to the specified one or more memory locations before returning control to the first thread.

15. An article comprising:

a tangible storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a processor, the instructions provide for;

loading data into locations of a memory resource and executing one or more monitor instruction for the locations;

reading the data from the memory structure, in a pre-specified order, responsive to determining that the data at one or more of the locations has been accessed by another thread;

wherein said determining further comprises polling of a status bit to determine whether the data at any of the data has been accessed by the other thread.

16. The article of claim 15, wherein said instructions further provide for:

reading only a portion of the data from the memory structure, responsive to determining that the data at the locations remains unmodified.

17. The article of claim 15, wherein:

said memory resource further comprises a local cache.

18. The article of claim 15, wherein said instructions that provide for said polling further provide for, when executed by a processor:

said polling is performed via execution of an architectural instruction.

19. The article of claim 15 wherein:

said status bit is part of a status register that may be read via execution of an architectural instruction.

20. The article of claim 15, wherein said one or more monitor instruction further comprises:

an architectural instruction to set the status bit responsive to a foreign write to one or more of the monitored locations.

21. The article of claim 15, wherein said one or more monitor instruction further comprises:

an architectural instruction to set the status bit responsive to eviction, due to a foreign read, of one or more of the monitored locations

22. An article comprising:

a tangible storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a processor, the instructions provide for;

executing via a first thread one or more instructions to register a handler module to be invoked in response to an access, via a second thread, to one or more specified memory locations;

transferring control to the handler module in response to an access, via the second thread, to one or more of the specified memory locations,

incrementing a counter; and

executing a deadlock policy responsive to the counter exceeding a maximum acceptable value.

23. The article of claim 22, wherein said instructions further provide for:

incrementing the counter responsive to each control transfer to the handler module.

24. The article of claim 22, wherein:

the counter is one of a plurality of counters, each counter being associated with a different instruction of the first thread; and

said instructions further provide that the counter is incremented responsive to determining that the handler module has been invoked from the instruction of the first thread.

25. The article of claim 22, wherein the instructions that provide for executing the deadlock policy further provide for, when executed by the processor:

comprises aborting execution of the first thread.

26. The article of claim 22, wherein the instructions that provide for executing the deadlock policy further provide for, when executed by the processor:

presenting a message to a user.

27. The article of claim 22, wherein the instructions further provide for, when executed by a processor:

returning control from the handler to the first thread.

28. The article of claim 27, wherein the instructions that provide for returning control from the handler to the first thread further comprise, when executed by the processor:

loading data to the specified one or more memory locations before returning control to the first thread.

29. A system, comprising:

a memory resource coupled to a first thread unit and a second thread unit;

the first thread unit including in its instruction set architecture one or more instructions to monitor specified locations of the memory resource;

wherein the instruction set architecture of the first thread unit further includes an instruction to set a status bit responsive to an access, by the second thread unit, to any of the specified locations; and

wherein the memory resource is further to store code that includes instructions to read data at all or part of the specified locations, depending on the value of the status bit.

30. A system, comprising:

a memory resource coupled to a first thread unit and a second thread unit;

the first thread unit including in its instruction set architecture an instruction to monitor a specified location of the memory resource;

wherein the instruction set architecture of the first thread unit further includes an instruction to invoke a handler module responsive to modification of data at said specified location; and

wherein the memory resource is further to store code that includes instructions to detect a potential deadlock condition.

31. The system of claim 30, wherein:

said instructions to detect a potential deadlock condition further comprise instructions to increment a counter responsive to invocation of the handler module.