Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories

• US 20090172308A1
• Filed: 04/08/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Pliant Technology, Inc. (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Granted Patent: US 8,775,717 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.

Claims

1. A flash memory controller comprising:

a plurality of processors, each processor including a register, an ALU and an internal memory;

a plurality of memories, at least some of the memories containing data structures, the data structures including metadata related to memory commands, at least some of the memories containing work queues for the plurality of processors;

a crossbar switch connecting the processors with the memories, the crossbar switch including a set of processor ports including one port for each processor and a set of memory ports including one port for each memory, and an internal switching mechanism allowing connection of any processor port with any memory port, but not allowing connection of a processor port with another processor port or a memory port with another memory port;

whereby a processor communicates with another processor by using the crossbar switch to place tasks on a work queue associated with the other processor.

2. The flash memory controller as in claim 1, further including:

an arbitrator that controls access to a crossbar switch memory port if more than one processor is seeking access to the port, the arbitrator controlling the crossbar switch internal switching circuitry to provide access to a processor that has won the arbitration.

3. The flash memory controller as in claim 1, in which:

at least one of the work queues contains a pointer to one of the data structures.

4. The flash memory controller as in claim 3, in which:

at least one of the memories contains a pointer to a data structure that is formatted to store metadata but includes one or more fields that do not currently store valid metadata.

5. The flash memory controller as in claim 1, in which:

at least one work queue is controlled by a set of registers, including a first register storing information from which an empty work queue can be distinguished from a work queue that contains at least one task; and

the controller further includes a signal connected to a processor, the signal being controlled by the first register, the signal being triggered by a transition between an empty work queue and a work queue containing a task, the signal causing the processor to terminate a sleep mode.

6. The method of operating a flash memory controller, comprising the following steps:

(a) receiving a host command specifying a read or write and a logical address;

(b) creating a metadata structure related to the host command, the structure specifying the host command and the logical address or an address related to the logical address;

(c) storing the metadata structure in a first memory or memory region;

(d) a first processor accessing a second memory or memory region, the second memory containing an ordered worklist associated with a second processor;

(e) the first processor writing a pointer to the metadata structure onto the worklist; and

(f) in response, the second processor performing a task relating to the metadata structure.

7. The method as in claim 6, in which

step (d) further includes the first processor accessing a crossbar switch and connecting to a port associated with the second memory.

8. The method as in claim 6, in which:

the step (f) second processor task includes the following substep;

(i) accessing the first memory or memory region and copying the metadata structure into a memory internal to the second processor.

9. The method as in claim 8, in which:

the step (f) act of accessing the first memory or memory region includes the second processor accessing a crossbar switch and connecting to a port associated with the first memory or memory region.

10. The method as in claim 8, in which:

the step (f) second processor task includes the following additional substeps;

(ii) modifying the contents of the metadata structure while the metadata structure is stored in the second processor internal memory; and

(iii) copying the modified metadata structure into the first memory.

11. A flash memory controller comprising:

a crossbar switch connecting a plurality of processors with a plurality of memories, including an arbitrator that assigns control of a memory port on the crossbar switch based on results of an arbitration;

the plurality of memories storing;

a plurality of populated metadata structures related to host commands;

lists of pointers to free metadata structures; and

a first and second worklist each containing pointers to populated metadata structures, each worklist being associated with a separate processor.

12. The controller as in claim 11, further including:

a first processor and a second processor, each processor including an ALU, a register and an internal processor memory, the internal processor memory of the first processor storing a first metadata structure relating to a first host command, the internal processor memory of the second processor storing a second metadata structure.

13. The controller as in claim 12, in which:

the first worklist is associated with the first processor and the second worklist is associated with the second processor;

a pointer on the first worklist points to a third metadata structure, the third metadata structure being stored in a controller memory, the third metadata structure relating to the first metadata structure; and

a pointer on the second worklist points to a fourth metadata structure, the fourth metadata structure being stored in a controller memory, the fourth metadata structure relating to the second metadata structure.

14. The controller as in claim 13, in which:

the first and second metadata structures are of a first type;

the third and fourth metadata structures are of a second type; and

the first metadata structure contains a pointer to the third metadata structure, and

the second metadata structure contains a pointer to the fourth metadata structure.

15. The controller as in claim 14, in which:

the third metadata structure contains a first logical address,

the fourth metadata structure contains a second logical address;

the first metadata structure contains a first physical address related to the first logical address; and

the second metadata structure contains a second physical address related to the second logical address.

16. A method of operating a flash storage controller, the flash storage controller including a first and second processor, a crossbar switch and first and second controller memories, the method comprising the following steps:

(a) the first processor storing a first metadata structure in a processor memory internal to the first processor;

(b) the first processor accessing a first crossbar switch port associated with the first controller memory;

(c) the first processor copying the first metadata structure to the first controller memory;

(d) the first processor accessing a second crossbar switch port associated with the second controller memory;

(e) the first processor placing a pointer to the first metadata structure in a worklist stored in the second controller memory, the worklist being associated with the second processor;

(f) the second processor accessing the first crossbar switch port;

(g) the second processor copying the first metadata structure from the first controller memory to a processor memory internal to the second processor; and

(h) the second processor modifying the first metadata structure.

17. The method as in claim 16, further including:

(i) the second processor populating fields of a second metadata structure, the second metadata structure located in the processor memory internal to the second processor; and

the step (h) modification includes adding a pointer to the second metadata structure to the first metadata structure.

18. The method as in claim 17, in which:

the first metadata structure includes a logical address; and

step (i) includes placing a first physical flash address in a second metadata structure field, the first physical flash address being related to the logical address.

19. The method as in claim 18, further including:

(j) the second processor populating fields of a third metadata structure, the third metadata structure located in the processor memory internal to the second processor; and

the step (h) modification includes adding a pointer to the third metadata structure to the first metadata structure.

20. The method as in claim 19, in which:

step (j) includes placing a second physical flash address in a third metadata structure field, the second physical flash address being related to the logical address.

21. A flash memory controller comprising:

a first processor and a second processor, each processor including a register, an ALU and an internal processor memory;

a first volatile memory containing a first worklist, the first worklist being associated with the first processor;

a second volatile memory containing a second worklist, the second worklist being associated with the second processor,

a third volatile memory containing a first metadata structure relating to a first host command;

a fourth volatile memory containing a second metadata structure relating to a second host command;

a crossbar switch including;

a set of processor ports, each connected to a processor, including a first processor port connected to the first processor and a second processor port connected to the second processor;

a set of memory ports, each connected to a volatile memory, including a first memory port connected to the first volatile memory, a second memory port connected to the second volatile memory and a third memory port connected to the third volatile memory and a fourth memory port connected to the fourth volatile memory;

the crossbar switch including internal circuitry selectively connecting one of the processor ports to one of the memory ports.

22. The controller as in claim 21, in which:

the first worklist contains first information related to the first host command and

the second worklist contains second information related to the second host command.

23. The controller as in claim 22, in which:

the first information constitutes a pointer to the first metadata structure; and

the second information constitutes a pointer to the second metadata structure.

24. The controller as in claim 23, in which:

the first worklist includes a pointer to a third metadata structure, the third metadata structure relating to the second host command.

25. The controller as in claim 23, in which:

the first and second metadata structures include a logical address, but do not include a physical address; and

the first processor internal processor memory includes a fourth metadata structure, the fourth metadata structure including a physical address.