Information processing apparatus and method of updating stack pointer

• US 20090172332A1
• Filed: 12/03/2008
• Published: 07/02/2009
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Suzuki, Hitoshi, Sato, Junichi, Ono, Rika
• Granted Patent: US 8,234,476 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block

Abstract

A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.

Claims

1. An information processing device, comprising:

an instruction execution part that outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory, and that outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer;

a memory protection information storage section that stores a memory protection information to define a plurality of partial spaces from the address space, the partial space being accessible by the instruction execution part;

a protection violation detection section that detects whether the access destination includes the plurality of the partial spaces, by collating the first information with the memory protection information stored in the memory protection information storage section; and

a checking section that checks whether the stack pointer point includes a predetermined partial space among the plurality of the partial spaces, by collating the second address information with the memory protection information stored in the memory protection information storage unit, the predetermined partial space being retained preliminarily as a stack area enabling the stack.

2. The information processing device according to claim 1, wherein the memory protection information includes a plurality of address range specified information and a stack identification information, the address range specified information specifies an address range of each of the plurality of the partial spaces, and the stack identification information indicates whether or not each of the plurality of the partial spaces corresponds to the stack area.

3. The information processing device according to claim 1, wherein the protection violation detection section includes a first collating circuit, the checking section includes a second collating circuit, the first collating circuit collates the memory protection information with the first address information, the second collating circuit collates the memory protection information with the second address information, and the first collating circuit and the second collating circuit are formed as a hardware independent from the instruction execution part.

4. The information processing device according to claim 1, further comprising a selector circuit that supplies the first address information or the second address information included in the access request selectively to the protection violation detection section,

wherein the second collating circuit is used also as the first collating circuit.

5. The information processing device according to claim 1, further comprising a stack pointer register that stores a current stack pointer value,

Wherein, by using having checked that an update stack pointer value is included in the stack area by the checking section as a cue, the stack pointer register stores the updated stack pointer value in order to complete an extension of the stack.

6. The information processing device according to claim 1, further comprising:

a stack pointer register that stores a current stack pointer value; and

an access control section that controls whether or not to permit the access to the memory based on the access request according to the detection result of the protection violation detection section,

wherein the instruction execution part supplies an SP (stack pointer) relative access information and the access request to the protection violation detection section by using a stack pointer value stored in the stack pointer register, the SP relative access information indicating whether the first address information has been generated or not,

wherein the access control section bans an access by the access request including the SP relative access information to a non-stack area based on a detecting result of the protection violation detection section.

7. The information processing device according to claim 1, wherein the first address information is specified by one of a single address, a combination of a base address and a size of data required to be transferred, and a combination of a lower bound address and an upper bound address of a location where the data required to be transferred is stored.

8. The information processing device according to claim 1, wherein the address range specified information comprises one of a combination of a lower bound address and an upper bound address, a combination of a starting address and an area size, and a starting address and a number of low-order bits to be masked.

9. The information processing device according to claim 1, wherein the starting address comprises one of a lower bound address and an upper bound address.

10. The information processing device according to claim 1, wherein the memory comprises at least one of a random access memory (RAM), a read only memory (ROM), and a flash memory.

12. The method of updating a stack pointer according to claim 7, further comprising

storing an updated stack pointer value to a stack pointer register storing a current stack pointer value, in order to complete an extension of the stack, by using having checked that an update stack pointer value is included in the stack area by the checking section as a cue.

11. A method of updating a stack pointer of an information processing device including an instruction executing part and a memory protection information storage section storing a memory protection information to specify a plurality of partial spaces which enable an access by the instruction executing part from an address space, the method comprising:

outputting an access request including a first address information to specify an access destination by the instruction executing part corresponding to an execution of an access request to the address space;

detecting whether the access destination is included in the plurality of the partial spaces, by collating the first address information with the memory protection information stored in the memory protection information storage section;

outputting a check request including a second address information to specify a stack pointer point after extension corresponding to an execution of a stack extension request to extend a stack included in the address space, by updating a stack pointer; and

checking whether the stack pointer point is included in a predetermined partial space among the plurality of the partial spaces, by collating the second address information with the memory protection information stored in the memory protection information storage section, the predetermined partial space being retained preliminarily as a stack area enabling the stack.