Instructions and logic to perform mask load and store operations

• US 20090172365A1
• Filed: 12/27/2007
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Orenstien, Doron, Sperber, Zeev, Eitan, Benny, Valentine, Bob
• Granted Patent: US 9,529,592 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a logic to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, wherein the mask move instruction is to be executed subject to mask information in a vector mask register.

2. The apparatus of claim 1, further comprising a register file including a plurality of extended registers each to store a vector data element including a plurality of packed data elements, and a control register to store the mask information.

3. The apparatus of claim 2, wherein the apparatus comprises a processor, the processor further including a memory subsystem having a store buffer including a plurality of entries each to store a pending instruction, a destination identifier, a source identifier, and, if the pending instruction is a mask store instruction, the mask information.

4. The apparatus of claim 1, wherein the mask move instruction is a mask load instruction including an opcode, a source identifier and a destination identifier, and wherein the logic is to access the vector mask register responsive to the mask load instruction to obtain the mask information.

5. The apparatus of claim 4, wherein the logic is to access a first bit of each of a plurality of fields of the vector mask register to obtain the mask information, wherein each first bit is a mask value for a corresponding one of the plurality of packed data elements of a vector data element.

6. The apparatus of claim 1, wherein the mask move instruction is a mask load instruction, and the logic is to execute a speculative full width load operation to obtain and store the vector data element into a temporary storage and then determine if an exception occurred during the execution.

7. The apparatus of claim 6, wherein if no exception occurred, the logic is to perform a propagated AND operation between each of a corresponding portion of the mask information and one of the plurality of packed data elements and store resulting data in the destination location.

8. The apparatus of claim 6, wherein if an exception occurred, the logic is to individually perform load operations to load unmasked portions of the vector data element to the destination location using a microcode handler.

9. The apparatus of claim 8, wherein the microcode handler is to determine if all of the mask information is of a second value and if not, individually load the unmasked portions, otherwise the microcode handler is to write zero values to the destination location.

10. A method comprising:

obtaining data including a plurality of packed values from a first storage of a system and storing the data in a destination storage of the system responsive to execution of a vector mask move instruction in a processor of the system.

11. The method of claim 10, further comprising speculatively obtaining and storing the data to a temporary storage as a full width load operation.

12. The method of claim 11, further comprising determining if an exception occurs during the full width load operation and if so, executing a handler to independently obtain and store each of the plurality of packed values in the destination storage.

13. The method of claim 12, further comprising only independently obtaining and storing each of the plurality of packed values having a corresponding portion of mask information associated with the vector mask move instruction having a first value, otherwise writing a zero value to the destination storage for the corresponding packed value.

14. The method of claim 10, further comprising speculatively performing a full width store operation responsive to the vector mask move instruction, the full width store operation including storage of an instruction field value, a source identifier, a destination identifier, and mask information associated with the vector mask move instruction in a store buffer, wherein the vector mask move instruction is a vector mask store instruction.

15. The method of claim 14, further comprising determining if an exception occurs during the full width store operation and if so, executing a handler to independently obtain and store each of the plurality of packed values in the destination storage.

16. The method of claim 15, further comprising only independently obtaining and storing each of the plurality of packed values having a corresponding portion of the mask information having a first value.

17. A machine-readable medium having stored thereon an instruction, which when executed by a machine causes the machine to perform a method comprising:

speculatively performing a full width move operation to obtain a vector data element including a plurality of packed values from a first storage, and store the vector data element in a destination storage, responsive to execution of the instruction, wherein the instruction is a vector mask move instruction subject to a mask.

18. The machine-readable medium of claim 17, wherein the instruction is a vector mask load instruction to load the vector data element from a memory location indicated by a source identifier associated with the vector mask load instruction to the destination storage indicated by a destination identifier associated with the vector mask load instruction, wherein the mask is stored in a vector mask register.

19. The machine-readable medium of claim 18, wherein the vector mask load instruction is to cause a processor to speculatively load the vector data element from the first storage to a temporary storage and to determine if an exception occurs during the speculative load, and if not to load unmasked portions of the vector data element to the destination storage.

20. The machine-readable medium claim 19, wherein the vector mask load instruction is to enable the processor to individually load unmasked ones of the packed values from the first storage to the destination storage if the exception occurs.

21. A system comprising:

a processor including an execution unit to execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source storage to a destination storage subject to mask information in a vector mask register, a register file including a plurality of vector registers each to store a vector data element and a control register to store a mask for the mask move instruction, and a store buffer including a plurality of entries each to store a pending instruction, a destination identifier, a source identifier, and, if the pending instruction is a mask store instruction, mask data from the mask; and

a dynamic random access memory (DRAM) coupled to the processor.

22. The system of claim 21, wherein the processor is to execute a speculative full width load operation to obtain and store the vector data element into a temporary storage and then determine if an exception occurred during the execution.

23. The system of claim 22, wherein the processor is to perform a propagated AND operation between each of a corresponding portion of the mask and one of the plurality of packed data elements and store resulting data in the destination storage if the exception did not occur, and otherwise to individually load unmasked portions of the vector data element from the source storage to the destination storage using a microcode handler.

24. The system of claim 21, wherein the processor is to speculatively perform a full width store operation to store the pending instruction, the source identifier, the destination identifier, and the mask data to the store buffer.

25. The system of claim 25, wherein the processor is to determine if an exception occurred during the full width store operation and if so, execute a handler to independently obtain and store each of the plurality of packed values having a corresponding portion of the mask data having a first value in the destination storage.