Enabling permute operations with flexible zero control

• US 20090172366A1
• Filed: 12/28/2007
• Published: 07/02/2009
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Valentine, Bob, Anderson, Cristina, Orenstien, Doron, Buxton, Mark
• Granted Patent: US 8,909,901 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 7/76 Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a logic to receive a permute instruction, first and second source operands, a first control value, and a second control value, and to perform a permute operation, wherein the logic is to store a selected portion of the first or second source operand or a zero value in a destination location based on an operation between a first portion of the first control value and at least a portion of the second control value.

2. The processor of claim 1, wherein the logic is to select a portion of the first source operand or the second source operand based on a second portion of the first control value.

3. The processor of claim 2, wherein the logic is to store the selected portion or the zero value for each of a plurality of elements of the destination location.

4. The processor of claim 3, wherein the logic is to perform the permute instruction on multiple lanes of vector data responsive to the permute instruction.

5. The processor of claim 3, wherein a result of the destination location is a lookup result of a table stored in memory.

6. The processor of claim 1, wherein the logic is to store the selected portion into a temporary storage location and to thereafter store the selected portion in the destination location based on a result of the operation.

7. The processor of claim 6, wherein the operation comprises a Boolean operation.

8. The processor of claim 1, further comprising a second logic to combine a result of the permute instruction with a result of a second permute instruction and to store the combined result in a second destination location.

9. The apparatus of claim 8, wherein the logic is to perform a permute operation using the combined result and a third source operand.

10. A machine-readable medium having stored thereon instructions, which when executed by a machine causes the machine to perform a method comprising:

performing a first pair of permute operations each responsive to a user-level permute instruction to obtain a first and second permuted result;

logically combining the first and second permuted results to obtain a first combined result;

performing at least one other permute operation responsive to a user-level permute instruction to obtain a third permuted result;

logically combining the first combined result and the third permuted result to obtain a final result.

11. The machine-readable medium of claim 10, wherein the final result corresponds to a lookup result from a table in memory.

12. The machine-readable medium of claim 10, wherein performing a first one of the pair of permute operations comprises receiving first and second source operands, a control operand, and an immediate value, and storing a selected portion of the first or second source operand or a zero value in a destination location based on an operation between a portion of the control operand and at least a portion of the immediate value.

13. The machine-readable medium of claim 12, wherein the method further comprises storing the selected portion into a temporary storage location and thereafter storing the selected portion in the destination location based on a result of the operation.

14. A method comprising:

performing a data sieve using a plurality of user-level permute instructions that execute using registers of a register file of a processor, to obtain a lookup result from a table stored in a storage coupled to the processor.

15. The method of claim 14, wherein each user-level permute instruction is to cause the processor to store a selected portion of a first or second source operand or a zero value in a destination location based on an operation between a first control value and at least a portion of immediate data associated with the user-level permute instruction.

16. The method of claim 15, further comprising selecting a portion of the first source operand or the second source operand based on a second control value associated with the user-level permute instruction, storing the selected portion into a temporary storage location, and thereafter storing the selected portion in the destination location based on a result of the operation.

17. The method of claim 14, further comprising logically combining first and second permuted results of first and second user-level permute instructions to obtain a first combined result, and logically combining the first combined result and a third permuted result of a third user-level permute instruction to obtain the lookup result.

18. A system comprising:

a processor including a first logic to generate a permuted result including a selected portion of a first or second source operand or a zero value for each element of a destination location responsive to a first permute instruction of a family of permute instructions, based on a comparison between a first control value and a second control value associated with the first permute instruction, and a second logic to combine the permuted result and a second permuted result of a second permute instruction of the family of permute instructions and to store the combined result in a second destination location; and

a dynamic random access memory (DRAM) coupled to the processor.

19. The system of claim 18, wherein the first logic is to select a portion of the first source operand or the second source operand based on a third control value associated with the first permute instruction, store the selected portion into a temporary storage location, and thereafter store the selected portion in the corresponding element of the destination location if the comparison results in a first value.

20. The system of claim 19, wherein the first logic is to store the zero value in the corresponding element of the destination location if the comparison results in a second value.

21. The system of claim 19, wherein the processor is to receive a plurality of permute instructions, each having first, second and third control values, and to perform an in-register lookup to a table stored in the DRAM.

22. The system of claim 21, wherein the second logic is to combine results of the plurality of permute instructions to generate a lookup result corresponding to an element from the table.

23. The system of claim 18, wherein different permute instructions of the family of permute instructions include different encodings to enable different zeroing behavior.

24. The system of claim 23, wherein the different encodings includes different immediate data values, wherein each of the immediate data values includes a second control value.