Digitally controlled dynamic power management unit for uninterruptible power supply

• US 20090172425A1
• Filed: 12/31/2007
• Published: 07/02/2009
• Est. Priority Date: 12/31/2007
• Status: Abandoned Application

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullivan, Patrick J., Cetin, Joseph A.
• Application Number:
  US12/006,229
• Publication Number:
  US 20090172425A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A memory system power management process includes providing a first level of power to operate a memory system while a primary power source is enabled, detecting an interruption of the primary power source, increasing a frequency of an oscillator driving a charge pump of a power converter providing the first level of power, and beginning a memory operation that increases a load on the power converter.

Claims

1. A power management system comprising:

a power converter; and

logic to increase an operating frequency of the power converter when a loss of primary power to a system comprising the power converter is detected.

2. The power management system of claim 1, wherein the power converter further comprises:

a charge pump comprising at least one flying capacitor driven by an oscillator.

3. A memory system comprising:

volatile and nonvolatile memory circuits;

a memory controller;

a power controller to provide power to at least the volatile and nonvolatile memory circuits; and

logic to cause an increase in the operating frequency of a power converter of the power controller prior to an imminent higher power operation on one or more of the volatile and nonvolatile memory circuits.

4. The memory system of claim 3, wherein the power converter further comprises:

a charge pump comprising at least one flying capacitor driven by an oscillator.

5. The memory system of claim 3, wherein the logic to cause an increase in the operating frequency of a power converter of the power controller prior to an imminent higher power operation further comprises:

logic to cause an increase in the operating frequency of a power converter of the power controller prior to an imminent backup of the volatile memory circuits to the nonvolatile memory circuits.

6. The memory system of claim 5, wherein the power converter further comprises:

a charge pump comprising at least one flying capacitor driven by an oscillator.

7. The memory system of claim 3, wherein the logic to cause an increase in the operating frequency of a power converter of the power controller prior to an imminent higher power operation further comprises:

logic to cause an increase in the operating frequency of at least one flying capacitor of the power controller prior to an imminent higher power operation.

8. The memory system of claim 3, further comprising:

primary and secondary power sources coupled to the power controller; and

logic to detect a loss of the primary power and to consequently operate the power controller using the secondary power, and to cause an increase in the operating frequency of a power converter of the power controller prior to an imminent higher power operation on one or more of the volatile and nonvolatile memory circuits as a result of the loss of primary power.

9. The memory system of claim 8, wherein the power converter further comprises:

a charge pump comprising at least one flying capacitor driven by an oscillator.

10. A memory system power management process comprising:

providing a first level of power to operate a memory system while a primary power source is enabled;

detecting an interruption of the primary power source;

increasing a frequency of an oscillator driving a charge pump of a power converter providing the first level of power; and

beginning a memory operation that increases a load on the power converter.

11. The memory system power management process of claim 10, wherein the beginning a memory operation that increases a load on the power converter further comprises:

beginning a backup of volatile memory to nonvolatile memory.

12. The memory system power management process of claim 10, further comprising:

operating the memory system using a backup power source upon interruption of the primary power source.

13. A power management system, comprising:

a power converter; and

logic to cause an increase in the operating frequency of the power converter prior to an imminent higher power operation involving a load supplied by the power converter.

14. The system of claim 13, wherein the power converter further comprises:

a charge pump comprising at least one flying capacitor driven by an oscillator.

15. The system of claim 13, wherein the logic to cause an increase in the operating frequency of a power converter prior to an imminent higher power operation further comprises:

logic to cause an increase in the operating frequency of at least one flying capacitor of the power converter prior to an imminent higher power operation.