STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER

• US 20090173967A1
• Filed: 01/04/2008
• Published: 07/09/2009
• Est. Priority Date: 01/04/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc., Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation, Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: Saenger, Katherine L., Yin, Haizhou, Hamaguchi, Masafumi, Hasumi, Ryoji
• Application Number:
  US11/969,618
• Publication Number:
  US 20090173967A1
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer. This invention also provides a twist-bonded semiconductor layer on a polycrystalline base layer, as well as methods for fabricating the aforementioned FETs.

Claims

1. A field effect transistor (FET) comprising a strained semiconductor channel located in a twist-bonded semiconductor layer and situated between spaced-apart source/drain (S/D) regions and under a gate stack, wherein a twist-bonded interface separates the twist-bonded semiconductor layer from an underlying substrate semiconductor layer, and at least some channel strain is induced by one or more local stress elements.

2. The FET of claim 1 wherein said one or more local stress elements are selected from the group including stress liner layers extending over the S/D regions and optionally extending over some part of the gate stack, embedded lattice-mismatched S/D regions, and a gate or gate stack with high intrinsic stress.

3. The FET of claim 1 wherein said twist-bonded semiconductor layer has a thickness from about 2 nm to about 100 nm.

4. The FET of claim 1 wherein the twist-bonded semiconductor layer comprises a material selected from single crystal Si, Si-based materials, Ge, III-V materials, and layered or embedded combinations of these materials.

5. The FET of claim 1 wherein the underlying substrate semiconductor layer comprises a material selected from single crystal Si, polycrystalline Si, Si-based materials, Ge, III-V materials, and layered or embedded combinations of these materials.

6. The FET of claim 1 wherein said underlying substrate semiconductor layer is a bulk semiconductor substrate or a semiconductor-on-insulator layer.

7. A semiconductor structure comprising a plurality of field effect transistors (FETs) each including at least a gate stack and S/D regions located on a substrate, wherein at least one of the FETs has a strained semiconductor channel disposed in a twist-bonded semiconductor layer located atop said substrate and at least some channel strain is induced by one or more local stress elements.

8. The semiconductor structure of claim 7 wherein said one or more local stress elements are selected from the group including stress liner layers extending over the S/D regions and optionally extending over some part of the gate stack, embedded lattice-mismatched S/D regions, and a gate or gate stack with high intrinsic stress.

9. The semiconductor structure of claim 7 wherein some of said plurality of FETs comprise at least one nFET and others of said plurality of FETs comprise at least one pFET both of which have channels in a (001) Si layer twist-bonded to an underling (001) Si layer.

10. The semiconductor structure of claim 7 wherein some of said plurality of FETs comprise at least one nFET in a non-twist-bonded (001) Si layer, and others of said plurality of FETs comprise at least one pFET in a (011) Si layer twist-bonded to an underlying (001) Si substrate layer.

11. A method for forming at least one field effect transistor (FET) on a twist-bonded semiconductor layer comprising:

forming a twist-bonded semiconductor layer on a base semiconductor layer; and

forming at least one FET on said twist-bonded semiconductor layer, wherein said forming said at least one FET includes forming at least one local stress element adjacent said at least one FET.

12. The method of claim 11 wherein said at least one local stress element is selected from the group including stress liner layers extending over S/D regions of said at least one FET and optionally extending over some part of a gate stack of said at least one FET, embedded lattice-mismatched S/D regions, and a gate or gate stack with high intrinsic stress.

13. The method of claim 11 wherein said twist-bonded semiconductor layer has a thickness from about 2 nm to about 100 nm.

14. The method of claim 11 wherein the twist-bonded semiconductor layer comprises a material selected from single crystal Si, Si-based materials, Ge, III-V materials, and layered or embedded combinations of these materials.

15. The method of claim 11 wherein the based semiconductor layer comprises a material selected from single crystal Si, polycrystalline Si, Ge, Si-based materials, III-V materials, and layered or embedded combinations of these materials.

16. The method of claim 11 wherein said base semiconductor layer is a bulk semiconductor substrate or a semiconductor-on-insulator layer.

17. The method of claim 11 wherein said at least one FET includes at least one nFET and at least one pFET, both of which are located on twist-bonded semiconductor layers.

18. A method for forming a plurality of FETs including at least one nFET and at least one pFET, the nFET on a non-twist-bonded (001) Si layer and the pFET on a twist-bonded (011) Si layer comprising:

forming a twist-bonded (011) Si layer on a (001) Si base substrate layer, said twist-bonded and base Si substrate layers separated by a twist-bonded interface;

amorphizing selected areas of the (011) Si layer to a depth below the twist-bonded interface and recrystallizing said amorphized areas to the orientation of the Si base substrate layer to produce changed-orientation (001) Si regions and original-orientation, twist-bonded (011) Si regions; and

forming at least one nFET on the changed-orientation (001) regions and at least one pFET on the original-orientation, twist-bonded (011) regions, said forming the at least one nFET and the at least one pFET including formation of at least one local stress element.

19. The method of claim 18 wherein said at least one local stress element is selected from the group including stress liner layers extending over S/D regions of said at least one nFET and said at least one pFET, and optionally extending over some part of a gate stack of said at least one nFET and said at least one pFET, embedded lattice-mismatched S/D regions, and a gate or gate stack with high intrinsic stress.

20. A method of forming a twist-bonded semiconductor layer on a semiconductor-on-insulator layer comprising:

selecting a starting substrate;

forming an insulating layer on said substrate;

forming a polycrystalline semiconductor layer on said insulating layer; and

bonding a single crystal semiconductor layer directly to said polycrystalline layer to form a twist-bonded layer on a twist-bonded interface.