Light-Sensing Device for Multi-Spectral Imaging

• US 20090173976A1
• Filed: 03/13/2009
• Published: 07/09/2009
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: Quantum Semiconductor LLC
• Original Assignee: Quantum Semiconductor LLC
• Inventors: AUGUSTO, Carlos J.R.P.
• Granted Patent: US 8,120,079 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14669 Infrared imagers
• CPC Class Codes: H01L 31/035254 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table, e.g. Si-SiGe superlattices
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Abstract

A method of fabricating multi-spectral photo-sensors including photo-diodes incorporating stacked epitaxial superlattices monolithically integrated with CMOS devices on a common semiconductor substrate.

Claims

1. A light-sensing device comprising a semiconductor substrate and photodiodes formed thereon, wherein the semiconductor substrate includes side-by-side active areas implanted therein and CMOS devices, said active areas having a defined polarity and said active areas being electrically isolated from one another and from the adjacent CMOS device by isolation regions (FOX), the photodiodes having a light-sensing region comprising a stack of layers with at least one superlattice region having interleaved well and barrier layers, wherein light can be absorbed in a first type of photodiode by the generation of electron-hole pairs through miniband-to-miniband transitions, and in a second type of photodiode by intersubband transitions, the photodiodes of the first and second types being formed in one single epitaxial growth step on said active areas.

2. A light-sensing device as claimed in claim 1, wherein the photodiodes of the first type are grown on active areas having a predetermined first polarity and the photodiodes of the second type being grown on active areas having a second polarity that is opposite to said first polarity.

3. A light-sensing device as claimed in claim 1, wherein the substrate is made of a material selected from the group comprising Silicon Bulk substrates, or Thick-Film Silicon-On-Insulator (SOI), or Thin-Film Silicon-On-Insulator (SOI), or Germanium Bulk substrates, or Thick-Film Germanium (GeOI), or Thin-Film Germanium-On-Insulator (GeOI).

4. A light-sensing device as claimed in claim 1, made on bulk substrates, wherein the active area underneath a photodiode is electrically connected to an adjacent CMOS device on a separate active area, wherein the source/drain regions of said CMOS device have the same polarity of the substrate surface underneath the photodiode epitaxial layers, wherein a portion of the source/drain region of said CMOS device and at least a portion of the substrate underneath said photodiode are electrically connected underneath the isolation region separating the two separate active areas by a well implant of the same polarity, and wherein said well having the same polarity of the substrate, is electrically isolated from said substrate by a deep-well of the opposite polarity.

5. A light-sensing device as claimed in claim 1, made on thick-film SOI substrates, wherein the active area underneath a photodiode is electrically connected to an adjacent CMOS device on a separate active area, wherein the source/drain regions of said CMOS device have the same polarity of the substrate surface underneath the photodiode epitaxial layers, wherein a portion of the source/drain region of said CMOS device and at least a portion of the substrate underneath said photodiode are electrically connected underneath the isolation region separating the two separate active areas by a well implant of the same polarity, and wherein the well implants of both polarities reach the buried oxide of the SOI substrate.

6. A light-sensing device as claimed in claim 5, wherein deep isolation trenches reaching the buried oxide of the SOI substrate provide complete dielectric isolation between adjacent photodiodes and/or CMOS devices.

7. A light-sensing device as claimed in claim 1, wherein the active areas are the bottom electrodes of epitaxially grown photodiodes.

8. A light-sensing device as claimed in claim 1 wherein the light-absorption region comprises a stack of superlattices, such as (Si_1-yC_y)_m—

(Ge)_n, or (Si)_m—

(Ge_1-zC_z)_n, or (Si_1-yC_y)_m—

(Ge_1-zC_z)_n, wherein a monotonically varying bandgap is produced by suitable changes in layer composition and/or superlattice periodicity.

9. A light-sensing device as claimed in claim 1 wherein the light-absorption region comprises a stack of superlattices, such as (Si_1-yC_y)_m—

(Ge)_n, or (Si)_m—

(Ge_1-zC_z)_n, or (Si_1-yC_y)_m—

(Ge_1-zC_z)_n, wherein a monotonically varying gap between subbands is produced by suitable changes in layer composition and/or superlattice periodicity.

10. A light-sensing device as claimed in claim 1 wherein the light-absorption region comprises a stack of superlattices, such as (Si_1-yC_y)_m—

(Ge)_n, or (Si)_m—

(Ge_1-zC_z)_n, or (Si_1-yC_y)_m—

(Ge_1-zC_z)_n, for photo-sensing through intersubband transitions with the same polarity of the active area underneath the epitaxial layers, and wherein the interface between the superlattice with the smallest bandgap and the layer underneath it, provides a barrier for lowest energy subbands, while allowing transport perpendicular to said interface of carriers that have been photo-excited.

11. A light-sensing device as claimed in claim 1, wherein the bottom electrode and the epitaxial layers comprising a middle region and a top electrode, form devices operating in avalanche mode, such as Avalanche Photo-Diodes diodes.

12. A light-sensing device as claimed in claim 1, wherein the region between the bottom electrode and the absorption layer is a bandgap and doping engineered avalanche multiplication region.

13. A light-sensing device as claimed in claim 12, wherein the avalanche multiplication region comprises at least one superlattice.

14. A light-sensing device as claimed in claim 12, wherein the avalanche multiplication region comprises doping impurities with deep energy levels in the bandgap of silicon, such as Indium and Tellurium.

15. A light-sensing device as claimed in claim 1, wherein the light absorption layers are patterned to form vertical nanowires, with dielectric isolation between said nanowires, with a contact to the top of said nanowires formed by a transparent conductive material.

16. A light-sensing device as claimed in claim 12, wherein the avalanche multiplication layers are patterned into vertical nanowires, with dielectric isolation between said nanowires.

17. A light-sensing device as claimed in claim 1, further comprising at least one heterojunction thermal device, fabricated with the same single epitaxial growth used for forming the photodiodes of the first and second types of photodiodes, wherein said heterojunction thermal device can be operated as a Heterojunction Integrated Thermionic (HIT) cooler device or as a thermoelectric power generator device.