SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20090173983A1
• Filed: 03/12/2009
• Published: 07/09/2009
• Est. Priority Date: 07/15/2005
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MORIKADO, Mutsuo, KUSUNOKI, Naoki
• Application Number:
  US12/402,920
• Publication Number:
  US 20090173983A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first conductivity type buried well formed in the semiconductor substrate;

a second conductivity type floating body region formed on the first conductivity type buried well;

a gate electrode formed above a first surface region of the second conductivity type floating body region via a gate insulating film;

first conductivity type source and drain regions, respectively, formed on second and third surface regions of the second conductivity type floating body region; and

a structure of increasing an electric capacity formed at an interface between the first conductivity type buried well and the second conductivity type floating body region.

2. The semiconductor device, as defined in claim 1, wherein:

the structure includes a recessed portion formed at a junction interface of the first conductivity type buried well relative to the second conductivity type floating body region.

3. The semiconductor device, as defined in claim 2, wherein:

the recessed portion is formed in accordance with the junction interface which is deeper at a portion below the gate electrode than at portions below the first conductivity type source and drain regions.

4. The semiconductor device, as defined in claim 2, wherein:

the recessed portion is of a width as at least twice as a width of a depletion layer from a side of the second conductivity floating body region, and a depth not smaller than the width of the depletion layer therefrom.

5. The semiconductor device, as defined in claim 2, wherein:

the recessed portion is of a substantially right angle at corners.

6. The semiconductor device, as defined in claim 2, wherein:

the recessed portion is of a round shape at corners.

7. The semiconductor device, as defined in claim 2, wherein:

the recessed portion is for a part of a concave and convex shape.

8. The semiconductor device, as defined in claim 2, wherein:

the first conductivity type buried well is formed by ion implantation in a multiple-step process includes a first step and a second step, an implantation depth in the second step being shallower than that in the first step.

9. The semiconductor device, as defined in claim 2, wherein:

the second conductivity type floating body region is formed by ion implantation in a multiple-step process includes a first step and a second step, an implantation depth in the second step being deeper than that in the first step.

10. The semiconductor device, as defined in claim 8, wherein:

a dosage in the second step is higher than that in the first step.

11. The semiconductor device, as defined in claim 9, wherein:

a dosage in the second step is higher than that in the first step.